SPI_DEVICE/2P Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.240m	14.577ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.760s	37.113us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.090s	46.907us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	14.460s	358.648us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.150s	1.564ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.210s	78.298us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.090s	46.907us	1	1	100.00
		spi_device_csr_aliasing	5.150s	1.564ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	23.143us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.320s	55.974us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.730s	14.293us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.900s	33.545us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.650s	16.769us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.370s	370.745us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.370s	370.745us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.860s	797.215us	1	1	100.00
		spi_device_tpm_sts_read	0.650s	18.283us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	0.670s	13.402us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	10.040s	5.039ms	1	1	100.00
		spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.740s	899.921us	1	1	100.00
		spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.740s	899.921us	1	1	100.00
		spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	10.100s	4.793ms	1	1	100.00
		spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	10.100s	4.793ms	1	1	100.00
		spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	10.100s	4.793ms	1	1	100.00
		spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	10.100s	4.793ms	1	1	100.00
		spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	10.100s	4.793ms	1	1	100.00
		spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.740s	567.536us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.790s	278.360us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.790s	278.360us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.790s	278.360us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.470s	8.866ms	1	1	100.00
		spi_device_read_buffer_direct	5.640s	670.789us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.790s	278.360us	1	1	100.00
		spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	4.743m	284.758ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.820s	1.473ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.820s	1.473ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.240m	14.577ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	44.930s	22.219ms	1	1	100.00
V2	stress_all	spi_device_stress_all	53.390s	7.764ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.660s	14.050us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.600s	37.546us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.380s	91.585us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.380s	91.585us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.760s	37.113us	1	1	100.00
		spi_device_csr_rw	1.090s	46.907us	1	1	100.00
		spi_device_csr_aliasing	5.150s	1.564ms	1	1	100.00
		spi_device_same_csr_outstanding	20.364s		0	1	0.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.760s	37.113us	1	1	100.00
		spi_device_csr_rw	1.090s	46.907us	1	1	100.00
		spi_device_csr_aliasing	5.150s	1.564ms	1	1	100.00
		spi_device_same_csr_outstanding	20.364s		0	1	0.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	1.010s	611.260us	1	1	100.00
		spi_device_tl_intg_err	4.250s	219.309us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	4.250s	219.309us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	53.360s	3.934ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test spi_device_same_csr_outstanding has 1 failures.

    • 0.spi_device_same_csr_outstanding.79183108120726506285093138097076123961060272240950153909228712105891856648394
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 18:24 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255