SRAM_CTRL/MAIN Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	45.960s	2.602ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.620s	43.456us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.650s	19.487us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	0.990s	31.171us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.680s	53.022us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.280s	369.970us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.650s	19.487us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	53.022us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.671m	230.283ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.686m	9.654ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.181m	82.585ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.416m	5.073ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	19.456m	25.743ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	17.960m	177.413ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	18.820s	5.168ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.790m	1.830ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.840s	715.119us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.882m	17.501ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	22.250s	1.519ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	10.140s	3.066ms	1	1	100.00
		sram_ctrl_throughput_w_readback	53.780s	944.451us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.131m	1.859ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.150s	1.162ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	33.275m	310.151ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.630s	22.099us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.140s	1.673ms	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.140s	1.673ms	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.620s	43.456us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	19.487us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	53.022us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.660s	55.733us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.620s	43.456us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	19.487us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	53.022us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.660s	55.733us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	15.250s	3.848ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.620s	1.062us	0	1	0.00
		sram_ctrl_tl_intg_err	1.770s	679.105us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.620s	1.062us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.770s	679.105us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.131m	1.859ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.131m	1.859ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.650s	19.487us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.790m	1.830ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.790m	1.830ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.790m	1.830ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	18.820s	5.168ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.610s	706.763us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	15.250s	3.848ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.410s	738.288us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	45.960s	2.602ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	45.960s	2.602ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.790m	1.830ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.620s	1.062us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	18.820s	5.168ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.620s	1.062us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.620s	1.062us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	45.960s	2.602ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.620s	1.062us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.820s	3.385ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.60519065649949199191679789587847737579816419137873393545137697991643004562362
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1062146 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1062146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---