SRAM_CTRL/RET Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.510s	148.754us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.640s	34.121us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	15.864s		0	1	0.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.630s	629.515us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.670s	55.937us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.800s	30.159us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	15.864s		0	1	0.00
		sram_ctrl_csr_aliasing	0.670s	55.937us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.440s	184.996us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.130s	204.078us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	4.264m	9.218ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.093m	11.793ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	27.106s		0	1	0.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.499m	5.450ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.580s	1.043ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.830m	35.419ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.570s	3.640ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.297m	10.743ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	9.370s	331.209us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	23.210s	256.244us	1	1	100.00
		sram_ctrl_throughput_w_readback	22.870s	226.744us	1	1	100.00
V2	regwen	sram_ctrl_regwen	56.370s	1.916ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.670s	84.971us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	20.271m	19.619ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.620s	36.699us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.970s	34.901us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.970s	34.901us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.640s	34.121us	1	1	100.00
		sram_ctrl_csr_rw	15.864s		0	1	0.00
		sram_ctrl_csr_aliasing	0.670s	55.937us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.700s	35.638us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.640s	34.121us	1	1	100.00
		sram_ctrl_csr_rw	15.864s		0	1	0.00
		sram_ctrl_csr_aliasing	0.670s	55.937us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.700s	35.638us	1	1	100.00
V2		TOTAL			16	17	94.12
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.020s	1.426ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.590s	7.409us	0	1	0.00
		sram_ctrl_tl_intg_err	1.780s	996.604us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.590s	7.409us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.780s	996.604us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	56.370s	1.916ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	56.370s	1.916ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	15.864s		0	1	0.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.830m	35.419ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.830m	35.419ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.830m	35.419ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.580s	1.043ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.850s	185.324us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.020s	1.426ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.770s	32.178us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.510s	148.754us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.510s	148.754us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.830m	35.419ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.590s	7.409us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.580s	1.043ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.590s	7.409us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.590s	7.409us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.510s	148.754us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.590s	7.409us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.915m	6.534ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 0.sram_ctrl_bijection.63866521560475188383277463253784203859817956733587228099058433703525715685170
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 18:20 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_csr_rw has 1 failures.

    • 0.sram_ctrl_csr_rw.88224755554681805949336700711403878422922580792872232392892946281483599429492
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 18:21 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.5067042142314539497596925028359010585170419447710613861887825449685293076556
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4468773ps failed at 4468773ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @   7408773 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7408773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]