bddb67a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 4.370s | 2.114ms | 1 | 1 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 1.770s | 2.485ms | 1 | 1 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 1.670s | 2.210ms | 1 | 1 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 2.360s | 2.534ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | sysrst_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| sysrst_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | TOTAL | 4 | 9 | 44.44 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 5.162m | 182.244ms | 1 | 1 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 1.165m | 77.306ms | 1 | 1 | 100.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 1.900s | 3.416ms | 1 | 1 | 100.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 6.510s | 4.381ms | 1 | 1 | 100.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 1.310s | 2.552ms | 1 | 1 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 2.110s | 2.123ms | 1 | 1 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 5.890s | 3.269ms | 1 | 1 | 100.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 4.540s | 2.613ms | 1 | 1 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 2.514m | 833.466ms | 1 | 1 | 100.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 56.940s | 32.979ms | 1 | 1 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 6.042m | 200.751ms | 1 | 1 | 100.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 2.280s | 2.016ms | 1 | 1 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 0 | 1 | 0.00 | ||
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| sysrst_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| sysrst_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| sysrst_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| sysrst_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| sysrst_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| sysrst_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 12 | 15 | 80.00 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 39.650s | 22.014ms | 1 | 1 | 100.00 |
| sysrst_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 11.930s | 6.071ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 18 | 27 | 66.67 |
Job killed most likely because its dependent job failed. has 9 failures:
Test sysrst_ctrl_tl_errors has 1 failures.
Test sysrst_ctrl_tl_intg_err has 1 failures.
Test sysrst_ctrl_intr_test has 1 failures.
Test sysrst_ctrl_csr_hw_reset has 1 failures.
Test sysrst_ctrl_csr_rw has 1 failures.
... and 4 more tests.
Job returned non-zero exit code has 1 failures:
cover_reg_top
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cover_reg_top/build.log
recompiling module tb
All of 82 modules done
Feature removed during lmreread, or wrong
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CPU time: 17.074 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1