UART Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke uart_smoke 0 1 0.00
V1 csr_hw_reset uart_csr_hw_reset 0 1 0.00
V1 csr_rw uart_csr_rw 0 1 0.00
V1 csr_bit_bash uart_csr_bit_bash 0 1 0.00
V1 csr_aliasing uart_csr_aliasing 0 1 0.00
V1 csr_mem_rw_with_rand_reset uart_csr_mem_rw_with_rand_reset 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr uart_csr_rw 0 1 0.00
uart_csr_aliasing 0 1 0.00
V1 TOTAL 0 6 0.00
V2 base_random_seq uart_tx_rx 0 1 0.00
V2 parity uart_smoke 0 1 0.00
uart_tx_rx 0 1 0.00
V2 parity_error uart_intr 0 1 0.00
uart_rx_parity_err 0 1 0.00
V2 watermark uart_tx_rx 0 1 0.00
uart_intr 0 1 0.00
V2 fifo_full uart_fifo_full 0 1 0.00
V2 fifo_overflow uart_fifo_overflow 0 1 0.00
V2 fifo_reset uart_fifo_reset 0 1 0.00
V2 rx_frame_err uart_intr 0 1 0.00
V2 rx_break_err uart_intr 0 1 0.00
V2 rx_timeout uart_intr 0 1 0.00
V2 perf uart_perf 0 1 0.00
V2 sys_loopback uart_loopback 0 1 0.00
V2 line_loopback uart_loopback 0 1 0.00
V2 rx_noise_filter uart_noise_filter 0 1 0.00
V2 rx_start_bit_filter uart_rx_start_bit_filter 0 1 0.00
V2 tx_overide uart_tx_ovrd 0 1 0.00
V2 rx_oversample uart_rx_oversample 0 1 0.00
V2 long_b2b_transfer uart_long_xfer_wo_dly 0 1 0.00
V2 stress_all uart_stress_all 0 1 0.00
V2 alert_test uart_alert_test 0 1 0.00
V2 intr_test uart_intr_test 0 1 0.00
V2 tl_d_oob_addr_access uart_tl_errors 0 1 0.00
V2 tl_d_illegal_access uart_tl_errors 0 1 0.00
V2 tl_d_outstanding_access uart_csr_hw_reset 0 1 0.00
uart_csr_rw 0 1 0.00
uart_csr_aliasing 0 1 0.00
uart_same_csr_outstanding 0 1 0.00
V2 tl_d_partial_access uart_csr_hw_reset 0 1 0.00
uart_csr_rw 0 1 0.00
uart_csr_aliasing 0 1 0.00
uart_same_csr_outstanding 0 1 0.00
V2 TOTAL 0 18 0.00
V2S tl_intg_err uart_sec_cm 0 1 0.00
uart_tl_intg_err 0 1 0.00
V2S sec_cm_bus_integrity uart_tl_intg_err 0 1 0.00
V2S TOTAL 0 2 0.00
V3 stress_all_with_rand_reset uart_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 0 27 0.00

Failure Buckets