CHIP Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: `bddb67a`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	14.397s		0	1	0.00
		chip_sw_example_rom	9.527s		0	1	0.00
		chip_sw_example_manufacturer	9.522s		0	1	0.00
		chip_sw_example_concurrency	9.561s		0	1	0.00
V1	csr_hw_reset	chip_csr_hw_reset	3.241m	6.769ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.147m	5.430ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	38.856m	43.355ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	47.789m	30.710ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	39.380s	2.210ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	47.789m	30.710ms	1	1	100.00
		chip_csr_rw	5.147m	5.430ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.060s	173.667us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	13.924s		0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	13.924s		0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	13.924s		0	1	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	13.332s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	13.332s		0	1	0.00
		chip_sw_uart_tx_rx_idx1	13.277s		0	1	0.00
		chip_sw_uart_tx_rx_idx2	13.071s		0	1	0.00
		chip_sw_uart_tx_rx_idx3	9.638s		0	1	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	14.155s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	14.581s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	14.848s		0	1	0.00
V1		TOTAL			5	18	27.78
V2	chip_pin_mux	chip_padctrl_attributes	2.297m	4.624ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.297m	4.624ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	9.608s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.668s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	9.717s		0	1	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.396m	3.952ms	1	1	100.00
		chip_tap_straps_testunlock0	6.793m	8.723ms	1	1	100.00
		chip_tap_straps_rma	32.141s		0	1	0.00
		chip_tap_straps_prod	1.363m	2.712ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	13.937s		0	1	0.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	9.764s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	9.556s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	9.556s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.676m	7.556ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	19.346m	15.404ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	14.235s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	14.350s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	43.564m	18.756ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.856m	2.901ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.708m	7.274ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.998m	2.953ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.839m	6.159ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.440m	2.872ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	3.905m	5.315ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.863m	2.638ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	30.731s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.535m	7.472ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.681m	5.205ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.942m	3.339ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.681m	5.205ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.557m	2.829ms	1	1	100.00
		chip_sw_aes_smoketest	2.072m	2.366ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.144m	2.392ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.387m	3.090ms	1	1	100.00
		chip_sw_csrng_smoketest	2.222m	3.241ms	1	1	100.00
		chip_sw_entropy_src_smoketest	8.705m	5.966ms	1	1	100.00
		chip_sw_gpio_smoketest	2.038m	2.886ms	1	1	100.00
		chip_sw_hmac_smoketest	2.586m	3.536ms	1	1	100.00
		chip_sw_kmac_smoketest	2.117m	2.747ms	1	1	100.00
		chip_sw_otbn_smoketest	1.745m		0	1	0.00
		chip_sw_pwrmgr_smoketest	2.493m	5.168ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.026m	6.289ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.451m	3.540ms	1	1	100.00
		chip_sw_rv_timer_smoketest	1.761m	2.806ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.919m	3.110ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.033m	2.700ms	1	1	100.00
		chip_sw_uart_smoketest	2.307m	2.586ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.460m	3.444ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.305m	3.705ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	9.844s		0	1	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	15.780s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	47.307s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.015m	3.836ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.500m	3.386ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	16.593s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	16.225s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.461m	2.858ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.461m	2.858ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	47.789m	30.710ms	1	1	100.00
		chip_same_csr_outstanding	18.318m	16.388ms	1	1	100.00
		chip_csr_hw_reset	3.241m	6.769ms	1	1	100.00
		chip_csr_rw	5.147m	5.430ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	47.789m	30.710ms	1	1	100.00
		chip_same_csr_outstanding	18.318m	16.388ms	1	1	100.00
		chip_csr_hw_reset	3.241m	6.769ms	1	1	100.00
		chip_csr_rw	5.147m	5.430ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	15.150s	293.164us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.300s	54.040us	1	1	100.00
		xbar_smoke_large_delays	41.790s	7.390ms	1	1	100.00
		xbar_smoke_slow_rsp	43.460s	5.534ms	1	1	100.00
		xbar_random_zero_delays	21.920s	484.335us	1	1	100.00
		xbar_random_large_delays	25.263s		0	1	0.00
		xbar_random_slow_rsp	3.743m	27.794ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	20.170s	301.115us	1	1	100.00
		xbar_error_and_unmapped_addr	12.810s	235.654us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	21.420s	486.427us	1	1	100.00
		xbar_error_and_unmapped_addr	12.810s	235.654us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	28.860s	1.148ms	1	1	100.00
		xbar_access_same_device_slow_rsp	5.782m	42.304ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	14.140s	784.607us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.860m	2.594ms	1	1	100.00
		xbar_stress_all_with_error	23.809s		0	1	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.792m	6.234ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.058m	834.397us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	15.780s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	30.311m	33.984ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.743s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	52.167s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	45.185s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	50.771s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	32.079s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	28.931s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	3.277m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	21.896s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	2.876m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	44.858s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.041s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	15.990s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	20.914s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	18.878s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	43.360s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	45.696s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	14.859s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.904m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.848s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.387s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	50.190s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	21.721s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	33.759s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	48.652s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.688s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.072m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.554s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	32.344s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	52.216s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.616s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	1.707m		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	26.760s		0	1	0.00
		rom_e2e_asm_init_dev	30.561s		0	1	0.00
		rom_e2e_asm_init_prod	2.362m		0	1	0.00
		rom_e2e_asm_init_prod_end	53.516s		0	1	0.00
		rom_e2e_asm_init_rma	1.533m		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	31.964m	15.893ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	31.595m	14.790ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	32.511m	14.762ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	33.106m	16.245ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	41.590m	34.980ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	41.590m	34.980ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.456m	3.069ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.856m	2.901ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.581m	3.229ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.426m	2.932ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	13.974m	8.897ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.298m	2.709ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	3.134m	4.346ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.759s		0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.129m	5.321ms	1	1	100.00
		chip_plic_all_irqs_10	4.177m	4.340ms	1	1	100.00
		chip_plic_all_irqs_20	4.780m	4.047ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	52.039s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.795s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.481m	4.291ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.797m	2.073ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	35.593s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.833m	8.553ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.064m	8.093ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.627m	8.095ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.881h	255.980ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.159m	4.068ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	2.493m	5.168ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.159m	4.068ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.213m	8.929ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.213m	8.929ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.435m	7.093ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.143m	5.689ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	35.552s		0	1	0.00
		chip_sw_aes_idle	2.426m	2.932ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.287m	3.370ms	1	1	100.00
		chip_sw_kmac_idle	28.340s		0	1	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.487m	3.818ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.356m	3.604ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	2.668m	4.493ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	34.082s		0	1	0.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	34.717s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	37.643s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.057m	4.743ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.924m	3.983ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.269m	4.704ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	4.922m	3.988ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.637m	4.963ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.676m	7.556ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	8.980m	10.570ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.924m	3.983ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.269m	4.704ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	14.235s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	14.350s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	43.564m	18.756ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.856m	2.901ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.708m	7.274ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.998m	2.953ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.839m	6.159ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.440m	2.872ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	3.905m	5.315ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.863m	2.638ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.557m	3.081ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	4.530m	4.555ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	36.899s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	48.847s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.958m	2.658ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.702m	2.944ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	12.839m	10.364ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.949m	3.014ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq			0	1	0.00
		chip_sw_flash_init_reduced_freq	12.607m	18.875ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	41.532s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.676m	7.556ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.943m	4.914ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	36.660s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.759s		0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	17.833m	8.553ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.191m	6.394ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.304m	3.742ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	4.947m	5.148ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	29.281s		0	1	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	45.478m	20.612ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.088m	2.667ms	1	1	100.00
		chip_sw_edn_entropy_reqs	8.668m	5.504ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.088m	2.667ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.191m	6.394ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.879m	3.182ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	14.830s		0	1	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.831s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	14.350s		0	1	0.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.545s		0	1	0.00
		chip_sw_flash_ctrl_ops_jitter_en	14.235s		0	1	0.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	14.404s		0	1	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	14.830s		0	1	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	14.349s		0	1	0.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	19.454m	10.568ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	13.808s		0	1	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	14.404s		0	1	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	13.808s		0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	13.808s		0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	13.808s		0	1	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	13.808s		0	1	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.759s		0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.210m	10.252ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	14.087s		0	1	0.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	4.817m	5.340ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	4.817m	5.340ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	1.692m	2.458ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.998m	2.953ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.287m	3.370ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.309m	2.861ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.516m	3.808ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	13.732s		0	1	0.00
		chip_sw_i2c_host_tx_rx_idx1	13.893s		0	1	0.00
		chip_sw_i2c_host_tx_rx_idx2	14.002s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	13.314s		0	1	0.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	19.454m	10.568ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.839m	6.159ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	21.939m	12.841ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	13.974m	8.897ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	23.998m	9.943ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.083m	2.883ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.825m	3.567ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.440m	2.872ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	19.454m	10.568ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.267s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.330m	3.474ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.299s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	28.340s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	3.134m	4.346ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.396m	3.952ms	1	1	100.00
		chip_tap_straps_rma	32.141s		0	1	0.00
		chip_tap_straps_prod	1.363m	2.712ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	14.460s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.267s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.267s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.267s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.216m	6.810ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	13.808s		0	1	0.00
		chip_sw_flash_rma_unlocked	14.404s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	9.973s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	9.972s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.084s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.347s		0	1	0.00
		chip_sw_lc_ctrl_transition	10.267s		0	1	0.00
		chip_sw_keymgr_key_derivation	19.454m	10.568ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.845m	9.902ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.838m	7.061ms	1	1	100.00
		chip_prim_tl_access	4.210m	10.252ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	8.980m	10.570ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	37.643s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.057m	4.743ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.924m	3.983ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.269m	4.704ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	4.922m	3.988ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.637m	4.963ms	1	1	100.00
		chip_tap_straps_dev	2.396m	3.952ms	1	1	100.00
		chip_tap_straps_rma	32.141s		0	1	0.00
		chip_tap_straps_prod	1.363m	2.712ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.005m	13.912ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	10.115s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	9.755s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	10.009s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	9.862s		0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	14.603s		0	1	0.00
		chip_rv_dm_lc_disabled	5.005m	13.912ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.647s		0	1	0.00
		chip_sw_lc_walkthrough_prod	14.271s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	14.974s		0	1	0.00
		chip_sw_lc_walkthrough_rma	14.286s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	14.603s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	14.493s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.957s		0	1	0.00
		rom_volatile_raw_unlock	1.340m		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	42.602m	16.827ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	43.564m	18.756ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	35.552s		0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	35.552s		0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	35.552s		0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	3.497m	3.938ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.267s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	14.830s		0	1	0.00
		chip_sw_otbn_mem_scramble	3.497m	3.938ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.454m	10.568ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.508m	4.233ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.638m	2.737ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	14.830s		0	1	0.00
		chip_sw_otbn_mem_scramble	3.497m	3.938ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.454m	10.568ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.508m	4.233ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.638m	2.737ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.267s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.162m	4.101ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	14.460s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	9.973s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	9.972s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.084s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.347s		0	1	0.00
		chip_sw_lc_ctrl_transition	10.267s		0	1	0.00
		chip_prim_tl_access	4.210m	10.252ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.210m	10.252ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	14.343s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.975s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.110m	25.151ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.115m	7.005ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.753m	10.058ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.114m	7.440ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.184m	22.925ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs			0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	7.213m	8.929ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs			0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.282m	4.801ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.975s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset			0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	25.337m	34.179ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.120m	5.238ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.576m		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1.594m		0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	43.699s		0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs	11.986m	9.640ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.313m	23.693ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.527m	2.698ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.759s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.845m	9.902ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.845m	9.902ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	11.986m	9.640ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	1.594m		0	1	0.00
		chip_sw_pwrmgr_wdog_reset	4.282m	4.801ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.493m	5.168ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	2.800m	3.775ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	10.028s		0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	14.600s		0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.795s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	13.638s		0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.759s		0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.064m	8.093ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.766m	5.029ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.433m	4.434ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	1.861m	2.387ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.638m	2.737ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	10.028s		0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	10.028s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	7.241m	9.811ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.183m	13.880ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	2.800m	3.775ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.882m	4.472ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.437m	6.539ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	32.141s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.005m	13.912ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.129m	5.321ms	1	1	100.00
		chip_plic_all_irqs_10	4.177m	4.340ms	1	1	100.00
		chip_plic_all_irqs_20	4.780m	4.047ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.727m	3.370ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.221m	2.754ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	15.780s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.865s		0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	14.240s		0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	13.794s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	14.452s		0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.508m	4.233ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	3.905m	5.315ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	4.528m	7.134ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	4.170m	6.490ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.838m	7.061ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.759s		0	1	0.00
		chip_sw_data_integrity_escalation	9.556s		0	1	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	43.699s		0	1	0.00
		chip_sw_sysrst_ctrl_reset	17.063m	23.426ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.887m	2.741ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.254m	3.568ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.496m	4.466ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.063m	23.426ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.063m	23.426ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	30.314m	21.132ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	30.314m	21.132ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.039m	6.117ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	41.590m	34.980ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	10.001s		0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	25.649s		0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	9.737s		0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	26.437s		0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	21.842s		0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	22.264s		0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	9.741s		0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	17.337s		0	1	0.00
V2		TOTAL			145	275	52.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.105m	2.644ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.149m	2.926ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	14.043s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.109m	6.028ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.510m	3.656ms	0	1	0.00
		rom_e2e_jtag_debug_dev	8.434m	13.560ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.517m		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.136m		0	1	0.00
		rom_e2e_jtag_inject_dev	2.725m		0	1	0.00
		rom_e2e_jtag_inject_rma	2.351m		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	21.757s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.090m	4.836ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	3.850m	2.736ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	16.215m	7.772ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	9.158m	5.959ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	44.018s		0	1	0.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	7.126m	4.520ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	14.081s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	13.761s		0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.215m	5.581ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.005m	4.818ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	11.986m	9.640ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.510m	3.656ms	0	1	0.00
		rom_e2e_jtag_debug_dev	8.434m	13.560ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.517m		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.275m	5.657ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.759s		0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.236h	38.510ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.236h	38.510ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	14.824s		0	1	0.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	13.332s		0	1	0.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	17.874s		0	1	0.00
V3		TOTAL			10	23	43.48
	Unmapped tests	chip_sival_flash_info_access	9.559s		0	1	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.696s		0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	13.863s		0	1	0.00
		chip_sw_otp_ctrl_descrambling	10.363s		0	1	0.00
		chip_sw_pwrmgr_lowpower_cancel	3.592m	3.990ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.101s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.687m	3.338ms	1	1	100.00
		TOTAL			163	325	50.15

Failure Buckets

Job returned non-zero exit code has 146 failures:

Test chip_sw_example_flash has 1 failures.

0.chip_sw_example_flash.77268710692212651747059119207804445237432316467651909091417881745236904172612
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp420991766643183305/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp420991766643183305/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp420991766643183305/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/sw/device/tests/BUILD:1748:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '//sw/device/tests:example_test_from_flash_sim_dv' failed; build aborted
  INFO: Elapsed time: 4.880s, Critical Path: 0.85s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.92569842935597380302879764359612646072655725714288195906445871099163130251087
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp2344133830946688679/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp2344133830946688679/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp2344133830946688679/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/sw/device/tests/BUILD:1758:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted
  INFO: Elapsed time: 0.080s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.13078007656802923848266285095340020369158667704042231579139741016699762702
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp1203040244395255698/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp1203040244395255698/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp1203040244395255698/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+hooks+manufacturer_test_hooks/BUILD.bazel:143:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted
  INFO: Elapsed time: 0.104s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_concurrency has 1 failures.

0.chip_sw_example_concurrency.58426725563266229089025516308766130439034766556101087173542628419492215163912
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp15854184041678023776/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp15854184041678023776/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp15854184041678023776/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/sw/device/tests/BUILD:1703:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '//sw/device/tests:example_concurrency_test_sim_dv' failed; build aborted
  INFO: Elapsed time: 0.080s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sival_flash_info_access has 1 failures.

0.chip_sival_flash_info_access.22611329450642909956195978395864557102555257874241597352464951189605801048840
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp11585396427759261810/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp11585396427759261810/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp11585396427759261810/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/sw/device/tests/BUILD:1844:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '//sw/device/tests:flash_ctrl_info_access_lc_sim_dv' failed; build aborted
  INFO: Elapsed time: 0.076s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 141 more tests.

Job timed out after * minutes has 4 failures:
- Test chip_sw_pwrmgr_main_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_main_power_glitch_reset.13587450673919656206002788623594771677539458728125916480756968983841442109045
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.95959633217057573940955332103330685438463132992313695953231657175257315483550
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
  Job timed out after 120 minutes
```
- Test chip_sw_pwrmgr_normal_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.44383174068198028322918769708454092250631548360307606859163707279105423529889
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log
```
  Job timed out after 120 minutes
```
- Test chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.8206789219807801200108445910977482614930443642604796285612737151436071193403
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.32741824828898574311385472657422625202742833389192298061824874521984421233616
    Line 457, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34980.489679 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34980.489679 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.26870433339804910989869152773588744927327448841352930444262119554208216489768
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2708.673416 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2708.673416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.77700477365411620384875799029534407250779826489676288644279373290304171528716
    Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2073.341410 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2073.341410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.99980504293501950172294253500093161607684352381721279708766671864589099917459
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2861.141000 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2861.141000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@133707) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.95778496398589621324625440759705907174979396173637070335741721788352702730712
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2857.570715 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@133707) { a_addr: 'h106f8  a_data: 'h3a3e6960  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h4  a_user: 'h1ae56  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2857.570715 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.10612108343028867428316735704472517654221638595426058519316879397106671875237
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2926.390510 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2926.390510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.105999773816434853441437679349786356953940558413901367422055109025707330794140
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3835.968000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3835.968000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.60104293443003511101500120614107331511193583487868510650086665342479276947066
    Line 408, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3385.817500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3385.817500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.42212796635167600533595823107367985314384519847551663360953048952382795245163
    Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 15404.071192 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 15404.071192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.35131888310219375770123670125850297554878680164994129501057666886993793735327
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 3656.059412 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3656.059412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.584714520454406451384492854675418909627090604197769490711296115666032894954
    Line 522, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 13559.895064 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 13559.895064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36935) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.45393053299874348451087294503300151401020566830296215958188630582529676883534
Line 223, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2209.654759 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36935) { a_addr: 'h10d4  a_data: 'h1e54ce75  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h1  a_user: 'h251ef  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2209.654759 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---