ADC_CTRL Simulation Results

Monday September 22 2025 19:22:52 UTC

GitHub Revision: b7bab30

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.030s	6.010ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.520s	799.870us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	0.840s	387.765us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.567m	45.849ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.060s	1.190ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	0.770s	742.969us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	0.840s	387.765us	1	1	100.00
		adc_ctrl_csr_aliasing	2.060s	1.190ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.006m	166.425ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.233m	326.805ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	3.271m	493.820ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	3.541m	487.747ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	10.776m	418.657ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.733m	200.741ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	3.087m	516.946ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.286m	162.325ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.330s	4.525ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	17.770s	34.061ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.604m	81.993ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	12.674m	496.381ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	0.980s	279.916us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	0.710s	360.959us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.550s	519.030us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.550s	519.030us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.520s	799.870us	1	1	100.00
		adc_ctrl_csr_rw	0.840s	387.765us	1	1	100.00
		adc_ctrl_csr_aliasing	2.060s	1.190ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	6.890s	4.161ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.520s	799.870us	1	1	100.00
		adc_ctrl_csr_rw	0.840s	387.765us	1	1	100.00
		adc_ctrl_csr_aliasing	2.060s	1.190ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	6.890s	4.161ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	7.520s	4.302ms	1	1	100.00
		adc_ctrl_tl_intg_err	8.790s	4.809ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	8.790s	4.809ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.050s	14.265ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00