EDN Simulation Results

Monday September 22 2025 19:22:52 UTC

GitHub Revision: b7bab30

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke			0	1	0.00
V1	csr_hw_reset	edn_csr_hw_reset	0.770s	15.299us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.750s	11.431us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.700s	3.562ms	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.930s	24.077us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.220s	96.549us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.750s	11.431us	1	1	100.00
		edn_csr_aliasing	0.930s	24.077us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	firmware	edn_genbits			0	1	0.00
V2	csrng_commands	edn_genbits			0	1	0.00
V2	genbits	edn_genbits			0	1	0.00
V2	interrupts	edn_intr			0	1	0.00
V2	alerts	edn_alert			0	1	0.00
V2	errs	edn_err			0	1	0.00
V2	disable	edn_disable			0	1	0.00
		edn_disable_auto_req_mode			0	1	0.00
V2	stress_all	edn_stress_all			0	1	0.00
V2	intr_test	edn_intr_test	0.710s	54.032us	1	1	100.00
V2	alert_test	edn_alert_test			0	1	0.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.090s	80.767us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.090s	80.767us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.770s	15.299us	1	1	100.00
		edn_csr_rw	0.750s	11.431us	1	1	100.00
		edn_csr_aliasing	0.930s	24.077us	1	1	100.00
		edn_same_csr_outstanding	0.820s	38.900us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.770s	15.299us	1	1	100.00
		edn_csr_rw	0.750s	11.431us	1	1	100.00
		edn_csr_aliasing	0.930s	24.077us	1	1	100.00
		edn_same_csr_outstanding	0.820s	38.900us	1	1	100.00
V2		TOTAL			3	11	27.27
V2S	tl_intg_err	edn_sec_cm			0	1	0.00
		edn_tl_intg_err	15.618s		0	1	0.00
V2S	sec_cm_config_regwen	edn_regwen			0	1	0.00
V2S	sec_cm_config_mubi	edn_alert			0	1	0.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm			0	1	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm			0	1	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm			0	1	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm			0	1	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert			0	1	0.00
		edn_sec_cm			0	1	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert			0	1	0.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	15.618s		0	1	0.00
V2S		TOTAL			0	3	0.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset			0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			8	21	38.10

Failure Buckets

• Job killed most likely because its dependent job failed. has 12 failures:

  • Test edn_smoke has 1 failures.

    • 0.edn_smoke.52291471101239090264664608421774242039360104348778104955831795297716786481287
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_smoke/latest/run.log

  • Test edn_regwen has 1 failures.

    • 0.edn_regwen.64253788031459365385813550739840419473825805085786949082155175301016529861802
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_regwen/latest/run.log

  • Test edn_genbits has 1 failures.

    • 0.edn_genbits.88329978576047939627866307847741638498416012306905270219002380892297710798686
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_genbits/latest/run.log

  • Test edn_stress_all has 1 failures.

    • 0.edn_stress_all.56066413746999670616648553454129660518930668658535938509301368776368282381768
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all/latest/run.log

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 0.edn_stress_all_with_rand_reset.36226715216469593175510126330100714113570235541204824834504408827939465218181
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

  • ... and 7 more tests.

• Job returned non-zero exit code has 2 failures:

  • Test default has 1 failures.

    • default
      Log /nightly/current_run/scratch/master/edn-sim-vcs/default/build.log

        recompiling module tb
        All of 91 modules done
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        CPU time: 19.616 seconds to compile
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
      

  • Test edn_tl_intg_err has 1 failures.

    • 0.edn_tl_intg_err.67958230699043287217073685645749117661287008343060392780442837390339155514312
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_tl_intg_err/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 19:25 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255