HMAC Simulation Results

Monday September 22 2025 19:22:52 UTC

GitHub Revision: b7bab30

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	10.170s	4.950ms	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.830s	19.463us	1	1	100.00
V1	csr_rw	hmac_csr_rw	0.780s	100.023us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	3.450s	113.541us	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	3.530s	112.278us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	1.290s	72.469us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.780s	100.023us	1	1	100.00
		hmac_csr_aliasing	3.530s	112.278us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	long_msg	hmac_long_msg	45.210s	5.252ms	1	1	100.00
V2	back_pressure	hmac_back_pressure	20.460s	546.498us	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	7.720s	191.788us	1	1	100.00
		hmac_test_sha384_vectors	17.680s	943.259us	1	1	100.00
		hmac_test_sha512_vectors	17.770s	217.199us	1	1	100.00
		hmac_test_hmac256_vectors	9.040s	313.431us	1	1	100.00
		hmac_test_hmac384_vectors	8.430s	713.755us	1	1	100.00
		hmac_test_hmac512_vectors	30.890s		0	1	0.00
V2	burst_wr	hmac_burst_wr	12.000s	1.285ms	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	1.915m	968.786us	1	1	100.00
V2	error	hmac_error	1.577m	12.120ms	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	1.265m	6.913ms	1	1	100.00
V2	save_and_restore	hmac_smoke	10.170s	4.950ms	1	1	100.00
		hmac_long_msg	45.210s	5.252ms	1	1	100.00
		hmac_back_pressure	20.460s	546.498us	1	1	100.00
		hmac_datapath_stress	1.915m	968.786us	1	1	100.00
		hmac_burst_wr	12.000s	1.285ms	1	1	100.00
		hmac_stress_all	3.517m	6.330ms	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	10.170s	4.950ms	1	1	100.00
		hmac_long_msg	45.210s	5.252ms	1	1	100.00
		hmac_back_pressure	20.460s	546.498us	1	1	100.00
		hmac_datapath_stress	1.915m	968.786us	1	1	100.00
		hmac_wipe_secret	1.265m	6.913ms	1	1	100.00
		hmac_test_sha256_vectors	7.720s	191.788us	1	1	100.00
		hmac_test_sha384_vectors	17.680s	943.259us	1	1	100.00
		hmac_test_sha512_vectors	17.770s	217.199us	1	1	100.00
		hmac_test_hmac256_vectors	9.040s	313.431us	1	1	100.00
		hmac_test_hmac384_vectors	8.430s	713.755us	1	1	100.00
		hmac_test_hmac512_vectors	30.890s		0	1	0.00
V2	wide_digest_configurable_key_length	hmac_smoke	10.170s	4.950ms	1	1	100.00
		hmac_long_msg	45.210s	5.252ms	1	1	100.00
		hmac_back_pressure	20.460s	546.498us	1	1	100.00
		hmac_datapath_stress	1.915m	968.786us	1	1	100.00
		hmac_burst_wr	12.000s	1.285ms	1	1	100.00
		hmac_error	1.577m	12.120ms	1	1	100.00
		hmac_wipe_secret	1.265m	6.913ms	1	1	100.00
		hmac_test_sha256_vectors	7.720s	191.788us	1	1	100.00
		hmac_test_sha384_vectors	17.680s	943.259us	1	1	100.00
		hmac_test_sha512_vectors	17.770s	217.199us	1	1	100.00
		hmac_test_hmac256_vectors	9.040s	313.431us	1	1	100.00
		hmac_test_hmac384_vectors	8.430s	713.755us	1	1	100.00
		hmac_test_hmac512_vectors	30.890s		0	1	0.00
		hmac_stress_all	3.517m	6.330ms	1	1	100.00
V2	stress_all	hmac_stress_all	3.517m	6.330ms	1	1	100.00
V2	alert_test	hmac_alert_test	0.570s	11.548us	1	1	100.00
V2	intr_test	hmac_intr_test	0.610s	12.519us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	1.050s	52.207us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	1.050s	52.207us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.830s	19.463us	1	1	100.00
		hmac_csr_rw	0.780s	100.023us	1	1	100.00
		hmac_csr_aliasing	3.530s	112.278us	1	1	100.00
		hmac_same_csr_outstanding	1.640s	58.492us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.830s	19.463us	1	1	100.00
		hmac_csr_rw	0.780s	100.023us	1	1	100.00
		hmac_csr_aliasing	3.530s	112.278us	1	1	100.00
		hmac_same_csr_outstanding	1.640s	58.492us	1	1	100.00
V2		TOTAL			16	17	94.12
V2S	tl_intg_err	hmac_sec_cm	0.720s	38.566us	1	1	100.00
		hmac_tl_intg_err	1.270s	316.672us	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	1.270s	316.672us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	10.170s	4.950ms	1	1	100.00
V3	stress_reset	hmac_stress_reset	2.740s	1.807ms	1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	51.880s	3.726ms	1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	1.010s	178.464us	1	1	100.00
		TOTAL			27	28	96.43

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test hmac_test_hmac512_vectors has 1 failures.

    • 0.hmac_test_hmac512_vectors.97959239813753659151963816587929385655222395158138951577261965642209787202765
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 19:26 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255