b7bab30| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 11.950s | 2.027ms | 1 | 1 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 20.060s | 11.254ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.690s | 36.182us | 1 | 1 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.600s | 43.101us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.060s | 115.680us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 0.950s | 147.729us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 0.780s | 82.344us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.600s | 43.101us | 1 | 1 | 100.00 |
| i2c_csr_aliasing | 0.950s | 147.729us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 7 | 7 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 0.690s | 17.826us | 0 | 1 | 0.00 |
| V2 | host_stress_all | i2c_host_stress_all | 2.091m | 52.601ms | 0 | 1 | 0.00 |
| V2 | host_maxperf | i2c_host_perf | 13.410s | 5.528ms | 1 | 1 | 100.00 |
| V2 | host_override | i2c_host_override | 0.640s | 27.318us | 1 | 1 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 2.723m | 4.273ms | 1 | 1 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 18.350s | 1.439ms | 1 | 1 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 0.740s | 389.468us | 1 | 1 | 100.00 |
| i2c_host_fifo_fmt_empty | 12.910s | 397.101us | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 1.840s | 131.699us | 1 | 1 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 2.112m | 6.642ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 19.020s | 2.569ms | 1 | 1 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.500s | 109.655us | 0 | 1 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 19.861s | 0 | 1 | 0.00 | |
| V2 | target_stress_all | i2c_target_stress_all | 25.510s | 82.968ms | 1 | 1 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 2.850s | 1.014ms | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 12.610s | 6.280ms | 1 | 1 | 100.00 |
| i2c_target_intr_smoke | 3.120s | 946.855us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 0.640s | 195.500us | 1 | 1 | 100.00 |
| i2c_target_fifo_reset_tx | 0.650s | 683.886us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 2.682m | 34.418ms | 1 | 1 | 100.00 |
| i2c_target_stress_rd | 12.610s | 6.280ms | 1 | 1 | 100.00 | ||
| i2c_target_intr_stress_wr | 3.050s | 5.120ms | 1 | 1 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 3.890s | 2.308ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 29.970s | 2.962ms | 1 | 1 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 3.690s | 1.234ms | 1 | 1 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 10.060s | 10.125ms | 0 | 1 | 0.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 1.540s | 648.361us | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 0.930s | 241.256us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 13.410s | 5.528ms | 1 | 1 | 100.00 |
| i2c_host_perf_precise | 1.690s | 216.997us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 19.020s | 2.569ms | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 1.010s | 52.406us | 0 | 1 | 0.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 2.000s | 541.149us | 1 | 1 | 100.00 |
| i2c_target_nack_acqfull_addr | 1.750s | 539.521us | 1 | 1 | 100.00 | ||
| i2c_target_nack_txstretch | 1.070s | 627.681us | 1 | 1 | 100.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 22.433s | 0 | 1 | 0.00 | |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 1.530s | 1.724ms | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.580s | 19.923us | 1 | 1 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.590s | 45.180us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.490s | 186.268us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.490s | 186.268us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.690s | 36.182us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.600s | 43.101us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 0.950s | 147.729us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.920s | 93.957us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.690s | 36.182us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.600s | 43.101us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 0.950s | 147.729us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.920s | 93.957us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 31 | 38 | 81.58 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.130s | 292.247us | 1 | 1 | 100.00 |
| i2c_sec_cm | 0.760s | 114.057us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.130s | 292.247us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 14.033s | 0 | 1 | 0.00 | |
| V3 | target_error_intr | i2c_target_unexp_stop | 1.230s | 1.384ms | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 3.730s | 685.301us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 40 | 50 | 80.00 |
Job returned non-zero exit code has 3 failures:
Test i2c_target_glitch has 1 failures.
0.i2c_target_glitch.50215543586325894318846878756284067043327732973358184933142080467320650174313
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:40 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_host_stress_all_with_rand_reset has 1 failures.
0.i2c_host_stress_all_with_rand_reset.66828567738153552606386019020061672656003099107857828705864262082992603776622
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:41 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_host_may_nack has 1 failures.
0.i2c_host_may_nack.106317118046005825272927267032045663723584487627155957894989849436016246487236
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_may_nack/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:41 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:
Test i2c_host_error_intr has 1 failures.
0.i2c_host_error_intr.89769227027419659804508828092742340106891849443886306073202955834805604729769
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 17825811 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 17825811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
0.i2c_target_stress_all_with_rand_reset.88436039860675769228149978557777586916784201306494079918716658928295876233983
Line 96, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 685300717 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 685300717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:
0.i2c_host_stress_all.89715865022796231564801405044253540464460505907093002682593020122984359785372
Line 120, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 52601011397 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @879747
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
0.i2c_target_unexp_stop.53192538577194601337006373813819364101712383742548976609451301432673263792309
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1383540795 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 33 [0x21])
UVM_INFO @ 1383540795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
0.i2c_target_hrst.48807248705595471041542919045509318858826981643167008322978467364586650691571
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10124609852 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10124609852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
0.i2c_host_mode_toggle.59782352354507505599398504685093200492373694117585428024152558769614257219710
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 109654687 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
0.i2c_target_tx_stretch_ctrl.27953007050281033932894480381850328628500228701084144788692938639753813256092
Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.