KMAC/MASKED Simulation Results

Monday September 22 2025 19:22:52 UTC

GitHub Revision: b7bab30

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	6.710s	445.089us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.920s	39.700us	1	1	100.00
V1	csr_rw	kmac_csr_rw	18.325s		0	1	0.00
V1	csr_bit_bash	kmac_csr_bit_bash	9.540s	295.206us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.270s	260.837us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.010s	85.841us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	18.325s		0	1	0.00
		kmac_csr_aliasing	3.270s	260.837us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.620s	38.918us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	0.930s	58.273us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	long_msg_and_output	kmac_long_msg_and_output	7.303m	8.065ms	1	1	100.00
V2	burst_write	kmac_burst_write	14.977m	13.766ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.705m	65.521ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.599s		0	1	0.00
		kmac_test_vectors_sha3_384	19.720m	181.435ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.957m	199.652ms	1	1	100.00
		kmac_test_vectors_shake_128	2.571m	36.495ms	1	1	100.00
		kmac_test_vectors_shake_256	19.728m	34.380ms	1	1	100.00
		kmac_test_vectors_kmac	2.340s	176.600us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.820s	275.425us	1	1	100.00
V2	sideload	kmac_sideload	5.274m	19.959ms	1	1	100.00
V2	app	kmac_app	27.040s	2.866ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	47.090s	15.097ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.379m	30.631ms	1	1	100.00
V2	error	kmac_error	2.129m	10.021ms	1	1	100.00
V2	key_error	kmac_key_error	7.120s	1.359ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.290s	106.284us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	18.268s		0	1	0.00
V2	entropy_mode_error	kmac_entropy_mode_error	24.213s		0	1	0.00
V2	entropy_ready_error	kmac_entropy_ready_error	35.890s	17.308ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.100s	123.082us	1	1	100.00
V2	stress_all	kmac_stress_all	27.816m	1.019s	1	1	100.00
V2	intr_test	kmac_intr_test	0.690s	39.904us	1	1	100.00
V2	alert_test	kmac_alert_test	0.680s	24.876us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.320s	30.767us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.320s	30.767us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.920s	39.700us	1	1	100.00
		kmac_csr_rw	18.325s		0	1	0.00
		kmac_csr_aliasing	3.270s	260.837us	1	1	100.00
		kmac_same_csr_outstanding	1.580s	140.238us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.920s	39.700us	1	1	100.00
		kmac_csr_rw	18.325s		0	1	0.00
		kmac_csr_aliasing	3.270s	260.837us	1	1	100.00
		kmac_same_csr_outstanding	1.580s	140.238us	1	1	100.00
V2		TOTAL			23	26	88.46
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.060s	42.177us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.060s	42.177us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.060s	42.177us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.060s	42.177us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.270s	174.718us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	26.200s	4.146ms	1	1	100.00
		kmac_tl_intg_err	3.220s	952.976us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.220s	952.976us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.100s	123.082us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	6.710s	445.089us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.274m	19.959ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.060s	42.177us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	26.200s	4.146ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	26.200s	4.146ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	26.200s	4.146ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	6.710s	445.089us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.100s	123.082us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	26.200s	4.146ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	37.650s	4.359ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	6.710s	445.089us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.587m	21.626ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			36	40	90.00

Failure Buckets

• Job returned non-zero exit code has 4 failures:

  • Test kmac_test_vectors_sha3_256 has 1 failures.

    • 0.kmac_test_vectors_sha3_256.29179069783694555781261447269858348270683293028627262121508381633792647137754
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 19:35 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test kmac_edn_timeout_error has 1 failures.

    • 0.kmac_edn_timeout_error.50474978239100570882495277991173417206864069378183163429386864226632368103054
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 19:36 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test kmac_entropy_mode_error has 1 failures.

    • 0.kmac_entropy_mode_error.100238196873468686313685513608433177478369502777920600659060389174362881653904
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 19:36 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test kmac_csr_rw has 1 failures.

    • 0.kmac_csr_rw.47046757838431263540402209561660488124484052788389084307676297704147391692924
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_rw/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 19:34 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255