b7bab30| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 16.470s | 1.448ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0.870s | 57.683us | 1 | 1 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 0.910s | 84.772us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 5.220s | 150.511us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 6.180s | 925.569us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 14.230s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0.910s | 84.772us | 1 | 1 | 100.00 |
| kmac_csr_aliasing | 6.180s | 925.569us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.640s | 14.993us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 0.890s | 16.897us | 1 | 1 | 100.00 |
| V1 | TOTAL | 7 | 8 | 87.50 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 28.405m | 405.884ms | 1 | 1 | 100.00 |
| V2 | burst_write | kmac_burst_write | 4.110m | 5.781ms | 1 | 1 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 13.921s | 0 | 1 | 0.00 | |
| kmac_test_vectors_sha3_256 | 28.040s | 8.112ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 18.640s | 1.650ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 11.496m | 41.595ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_128 | 24.607m | 304.764ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_256 | 3.218m | 22.583ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac | 1.260s | 29.838us | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 1.790s | 338.805us | 1 | 1 | 100.00 | ||
| V2 | sideload | kmac_sideload | 3.340m | 16.561ms | 1 | 1 | 100.00 |
| V2 | app | kmac_app | 2.710m | 14.590ms | 1 | 1 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 1.208m | 4.529ms | 1 | 1 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 20.110s | 698.602us | 1 | 1 | 100.00 |
| V2 | error | kmac_error | 19.824s | 0 | 1 | 0.00 | |
| V2 | key_error | kmac_key_error | 2.640s | 2.689ms | 1 | 1 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 19.879s | 0 | 1 | 0.00 | |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 18.770s | 1.641ms | 1 | 1 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 7.630s | 791.227us | 1 | 1 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 3.750s | 1.755ms | 1 | 1 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 0.940s | 89.825us | 1 | 1 | 100.00 |
| V2 | stress_all | kmac_stress_all | 16.412m | 125.341ms | 1 | 1 | 100.00 |
| V2 | intr_test | kmac_intr_test | 0.710s | 27.733us | 1 | 1 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.690s | 27.851us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 1.150s | 89.233us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 1.150s | 89.233us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0.870s | 57.683us | 1 | 1 | 100.00 |
| kmac_csr_rw | 0.910s | 84.772us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 6.180s | 925.569us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 20.352s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0.870s | 57.683us | 1 | 1 | 100.00 |
| kmac_csr_rw | 0.910s | 84.772us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 6.180s | 925.569us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 20.352s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 22 | 26 | 84.62 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.630s | 142.450us | 1 | 1 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.630s | 142.450us | 1 | 1 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.630s | 142.450us | 1 | 1 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.630s | 142.450us | 1 | 1 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.530s | 749.901us | 1 | 1 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 27.140s | 22.071ms | 1 | 1 | 100.00 |
| kmac_tl_intg_err | 2.800s | 107.300us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 2.800s | 107.300us | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 0.940s | 89.825us | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 16.470s | 1.448ms | 1 | 1 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 3.340m | 16.561ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.630s | 142.450us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 27.140s | 22.071ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 27.140s | 22.071ms | 1 | 1 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 27.140s | 22.071ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 16.470s | 1.448ms | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 0.940s | 89.825us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 27.140s | 22.071ms | 1 | 1 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 59.960s | 8.043ms | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 16.470s | 1.448ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.372m | 6.772ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 35 | 40 | 87.50 |
Job returned non-zero exit code has 5 failures:
Test kmac_sideload_invalid has 1 failures.
0.kmac_sideload_invalid.108399732542452011037343417350302741437847355632292234472161004462553979033390
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:44 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_test_vectors_sha3_224 has 1 failures.
0.kmac_test_vectors_sha3_224.5290093163239344544853517104218971748473146246738983899838967873055402318299
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:44 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_error has 1 failures.
0.kmac_error.85954043684123860262861964965965696528761262780684699885859962116578682161210
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_error/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:44 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_same_csr_outstanding has 1 failures.
0.kmac_same_csr_outstanding.66945483949721777637199201208313757912100338667116505378039865220525755608251
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:45 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_csr_mem_rw_with_rand_reset has 1 failures.
0.kmac_csr_mem_rw_with_rand_reset.80051683451198298461552086594236302669200975337348966452536350697551107942431
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:45 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255