b7bab30| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 30.000s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 1.000s | 107.286us | 1 | 1 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 37.000s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 30.000s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | pattgen_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 29.000s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 37.000s | 0 | 1 | 0.00 | |
| pattgen_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |||
| V1 | TOTAL | 1 | 6 | 16.67 | |||
| V2 | perf | pattgen_perf | 38.000s | 0 | 1 | 0.00 | |
| V2 | cnt_rollover | cnt_rollover | 25.000s | 0 | 1 | 0.00 | |
| V2 | error | pattgen_error | 18.000s | 0 | 1 | 0.00 | |
| V2 | stress_all | pattgen_stress_all | 29.000s | 0 | 1 | 0.00 | |
| V2 | alert_test | pattgen_alert_test | 1.000s | 33.247us | 1 | 1 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 17.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 2.000s | 140.473us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 2.000s | 140.473us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 1.000s | 107.286us | 1 | 1 | 100.00 |
| pattgen_csr_rw | 37.000s | 0 | 1 | 0.00 | |||
| pattgen_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |||
| pattgen_same_csr_outstanding | 30.000s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 1.000s | 107.286us | 1 | 1 | 100.00 |
| pattgen_csr_rw | 37.000s | 0 | 1 | 0.00 | |||
| pattgen_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |||
| pattgen_same_csr_outstanding | 30.000s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 2 | 8 | 25.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 38.000s | 0 | 1 | 0.00 | |
| pattgen_sec_cm | 1.000s | 164.744us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 38.000s | 0 | 1 | 0.00 | |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 29.000s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 21.000s | 0 | 1 | 0.00 | ||
| TOTAL | 4 | 18 | 22.22 |
Job returned non-zero exit code has 14 failures:
Test pattgen_smoke has 1 failures.
0.pattgen_smoke.97258932104279141839112655528216015662370378717254798139678434190486557027183
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 22, 2025 at 19:29:47 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test pattgen_perf has 1 failures.
0.pattgen_perf.89456025763243510101763467771456087339302466303395387174034848821378206854385
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 22, 2025 at 19:29:56 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test pattgen_error has 1 failures.
0.pattgen_error.45285021591827192707603865675153112427800128585381106208485918604634055603177
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_error/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 22, 2025 at 19:29:38 UTC (total: 00:00:18)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test cnt_rollover has 1 failures.
0.cnt_rollover.102047095585072641655561572499293250978354117005373833079378132335683300543410
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.cnt_rollover/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 22, 2025 at 19:29:45 UTC (total: 00:00:25)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test pattgen_inactive_level has 1 failures.
0.pattgen_inactive_level.73574001462664956469091333166162897023767478966185736987187857127113291033337
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 22, 2025 at 19:29:41 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 9 more tests.