b7bab30| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | prim_alert_request_test | prim_async_alert | 0 | 1 | 0.00 | ||
| prim_async_fatal_alert | 0.490s | 28.706us | 0 | 1 | 0.00 | ||
| prim_sync_alert | 0.410s | 10.607us | 1 | 1 | 100.00 | ||
| prim_sync_fatal_alert | 0.550s | 28.028us | 1 | 1 | 100.00 | ||
| V1 | prim_alert_test | prim_async_alert | 0 | 1 | 0.00 | ||
| prim_async_fatal_alert | 0.490s | 28.706us | 0 | 1 | 0.00 | ||
| prim_sync_alert | 0.410s | 10.607us | 1 | 1 | 100.00 | ||
| prim_sync_fatal_alert | 0.550s | 28.028us | 1 | 1 | 100.00 | ||
| V1 | prim_alert_ping_request_test | prim_async_alert | 0 | 1 | 0.00 | ||
| prim_async_fatal_alert | 0.490s | 28.706us | 0 | 1 | 0.00 | ||
| prim_sync_alert | 0.410s | 10.607us | 1 | 1 | 100.00 | ||
| prim_sync_fatal_alert | 0.550s | 28.028us | 1 | 1 | 100.00 | ||
| V1 | prim_alert_integrity_errors_test | prim_async_alert | 0 | 1 | 0.00 | ||
| prim_async_fatal_alert | 0.490s | 28.706us | 0 | 1 | 0.00 | ||
| prim_sync_alert | 0.410s | 10.607us | 1 | 1 | 100.00 | ||
| prim_sync_fatal_alert | 0.550s | 28.028us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 2 | 4 | 50.00 | |||
| V2 | prim_alert_init_trigger_test | prim_async_alert | 0 | 1 | 0.00 | ||
| prim_async_fatal_alert | 0.490s | 28.706us | 0 | 1 | 0.00 | ||
| prim_sync_alert | 0.410s | 10.607us | 1 | 1 | 100.00 | ||
| prim_sync_fatal_alert | 0.550s | 28.028us | 1 | 1 | 100.00 | ||
| Unmapped tests | prim_async_fatal_alert_with_3_cycles_skew | 20.021s | 0 | 1 | 0.00 | ||
| TOTAL | 2 | 5 | 40.00 |
Job returned non-zero exit code has 2 failures:
Test default has 1 failures.
default
Log /nightly/current_run/scratch/master/prim_alert-sim-vcs/default/build.log
recompiling module prim_alert_tb
All of 25 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 6.631 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Test prim_async_fatal_alert_with_3_cycles_skew has 1 failures.
0.prim_async_fatal_alert_with_3_cycles_skew.31884014621732203848285388053148391623656644333546334460505082893173497436478
Log /nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_async_fatal_alert_with_3_cycles_skew/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:25 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Job killed most likely because its dependent job failed. has 1 failures:
Offending '$rose(alert_tx_o.alert_p)' has 1 failures:
0.prim_async_fatal_alert.28972181253704754940816204082430374335515706609142003257599219137547962524286
Line 87, in log /nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest/run.log
Offending '$rose(alert_tx_o.alert_p)'
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv(334) @ 25986000: reporter [ASSERT FAILED] PingHs_A
[prim_alert_seq] Ping request sequence[4] finished!
[prim_alert_seq] Ping request sequence[5] finished!
[prim_alert_seq] Ping request sequence[6] finished!