b7bab30| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| Unmapped tests | prim_lfsr_fib_smoke | 22.813s | 0 | 1 | 0.00 | ||
| prim_lfsr_fib_test | 20.015s | 0 | 1 | 0.00 | |||
| prim_lfsr_gal_test | 2.679m | 336.688ms | 1 | 1 | 100.00 | ||
| prim_lfsr_gal_smoke | 1.170s | 1.436ms | 1 | 1 | 100.00 | ||
| TOTAL | 2 | 4 | 50.00 |
Job returned non-zero exit code has 2 failures:
Test prim_lfsr_fib_smoke has 1 failures.
0.prim_lfsr_fib_smoke.92654726415435733134190802624975725524323481061504700293793390021181286013627
Log /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:24 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test prim_lfsr_fib_test has 1 failures.
0.prim_lfsr_fib_test.87700217976839664573692728463389677607429596563395779859329946243850797024225
Log /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255