b7bab30| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | rom_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| rom_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | mem_walk | rom_ctrl_mem_walk | 0 | 1 | 0.00 | ||
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 0 | 1 | 0.00 | ||
| V1 | TOTAL | 0 | 8 | 0.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 0 | 1 | 0.00 | ||
| V2 | stress_all | rom_ctrl_stress_all | 0 | 1 | 0.00 | ||
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 0 | 1 | 0.00 | ||
| V2 | alert_test | rom_ctrl_alert_test | 0 | 1 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 0 | 6 | 0.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 0 | 1 | 0.00 | ||
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | tl_intg_err | rom_ctrl_sec_cm | 0 | 1 | 0.00 | ||
| rom_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 0 | 1 | 0.00 | ||
| V2S | prim_count_check | rom_ctrl_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 1 | 0.00 | ||
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 1 | 0.00 | ||
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 1 | 0.00 | ||
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 1 | 0.00 | ||
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 1 | 0.00 | ||
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 0 | 1 | 0.00 | ||
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 0 | 1 | 0.00 | ||
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 0 | 1 | 0.00 | ||
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 1 | 0.00 | ||
| rom_ctrl_kmac_err_chk | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 0 | 1 | 0.00 | ||
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 1 | 0.00 | ||
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 0 | 1 | 0.00 | ||
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 0 | 4 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 0 | 19 | 0.00 |
Job killed most likely because its dependent job failed. has 19 failures:
Test rom_ctrl_smoke has 1 failures.
Test rom_ctrl_stress_all has 1 failures.
Test rom_ctrl_max_throughput_chk has 1 failures.
Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
Test rom_ctrl_kmac_err_chk has 1 failures.
... and 14 more tests.
Job returned non-zero exit code has 1 failures:
default
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/default/build.log
recompiling module rom_ctrl_fsm_if
All of 115 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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CPU time: 15.783 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Job timed out after * minutes has 1 failures:
cover_reg_top
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/cover_reg_top/build.log
Job timed out after 60 minutes