RV_TIMER Simulation Results

Monday September 22 2025 19:22:52 UTC

GitHub Revision: b7bab30

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.690s	566.000us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.550s	57.105us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.550s	24.535us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.500s	437.619us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.670s	42.554us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.060s	30.452us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.550s	24.535us	1	1	100.00
		rv_timer_csr_aliasing	0.670s	42.554us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	7.210s	6.871ms	0	1	0.00
V2	disabled	rv_timer_disabled	0.990s	531.270us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	8.803m	486.731ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	8.803m	486.731ms	1	1	100.00
V2	stress	rv_timer_stress_all	0.520s	162.913us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.530s	11.300us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.550s	106.608us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.820s	482.503us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.820s	482.503us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.550s	57.105us	1	1	100.00
		rv_timer_csr_rw	0.550s	24.535us	1	1	100.00
		rv_timer_csr_aliasing	0.670s	42.554us	1	1	100.00
		rv_timer_same_csr_outstanding	0.730s	41.765us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.550s	57.105us	1	1	100.00
		rv_timer_csr_rw	0.550s	24.535us	1	1	100.00
		rv_timer_csr_aliasing	0.670s	42.554us	1	1	100.00
		rv_timer_same_csr_outstanding	0.730s	41.765us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.680s	38.683us	1	1	100.00
		rv_timer_tl_intg_err	1.130s	912.591us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.130s	912.591us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	18.577s		0	1	0.00
V3	max_value	rv_timer_max	1.160s	610.660us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.220s	92.612us	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• Job returned non-zero exit code has 1 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.108046660264806480502849322625831957894246687843656246259765970440223742889453
      Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 19:33 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.6689432559609240864723209211851843998926607068962542884609996132698264682888
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 610659676 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 610659676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.73904981353075848721341146777590393870463653657885530007986328482218090135091
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 6871170700 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9f5d0304) == 0x1
        UVM_INFO @ 6871170700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---