SPI_DEVICE/1R1W Simulation Results

Monday September 22 2025 19:22:52 UTC

GitHub Revision: b7bab30

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.200s	1.428ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.900s	30.448us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	0.970s	61.576us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	14.180s	5.025ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	9.060s	410.119us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.170s	166.806us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	0.970s	61.576us	1	1	100.00
		spi_device_csr_aliasing	9.060s	410.119us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.590s	12.830us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	0.980s	33.226us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.700s	31.464us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.660s	6.187us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.630s	5.750us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.870s	304.307us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.870s	304.307us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.070s	1.048ms	1	1	100.00
		spi_device_tpm_sts_read	0.860s	137.160us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.980s	5.357ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.670s	220.076us	1	1	100.00
		spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.160s	1.015ms	1	1	100.00
		spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.160s	1.015ms	1	1	100.00
		spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	13.763s		0	1	0.00
		spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	13.763s		0	1	0.00
		spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	13.763s		0	1	0.00
		spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	13.763s		0	1	0.00
		spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	13.763s		0	1	0.00
		spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	9.370s	26.723ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	12.740s	7.087ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	12.740s	7.087ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	12.740s	7.087ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.530s	281.324us	1	1	100.00
		spi_device_read_buffer_direct	7.940s	1.107ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	12.740s	7.087ms	1	1	100.00
		spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.134m	56.625ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.860s	205.147us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.860s	205.147us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.200s	1.428ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.138m	11.915ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.341m	27.475ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.610s	26.866us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.630s	45.460us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.420s	54.279us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.420s	54.279us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.900s	30.448us	1	1	100.00
		spi_device_csr_rw	0.970s	61.576us	1	1	100.00
		spi_device_csr_aliasing	9.060s	410.119us	1	1	100.00
		spi_device_same_csr_outstanding	1.440s	309.136us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.900s	30.448us	1	1	100.00
		spi_device_csr_rw	0.970s	61.576us	1	1	100.00
		spi_device_csr_aliasing	9.060s	410.119us	1	1	100.00
		spi_device_same_csr_outstanding	1.440s	309.136us	1	1	100.00
V2		TOTAL			19	22	86.36
V2S	tl_intg_err	spi_device_sec_cm	0.940s	93.592us	1	1	100.00
		spi_device_tl_intg_err	13.650s	802.545us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.650s	802.545us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	44.790s	24.250ms	1	1	100.00
		TOTAL			30	33	90.91

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.67097480275370657467306733965120071155946713252193778602095032810705972179258
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3687445 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[58])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3687445 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3687445 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[954])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.88974318551539289966852907117493326186600179306196287521677101693015713522247
      Line 83, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2873247 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe42b93 [111001000010101110010011] vs 0x0 [0])
        UVM_ERROR @   2894247 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3bb094 [1110111011000010010100] vs 0x0 [0])
        UVM_ERROR @   2980247 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc79cdb [110001111001110011011011] vs 0x0 [0])
        UVM_ERROR @   3050247 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe6a121 [111001101010000100100001] vs 0x0 [0])
        UVM_ERROR @   3116247 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd73e92 [110101110011111010010010] vs 0x0 [0])
      

• Job returned non-zero exit code has 1 failures:

  • Test spi_device_intercept has 1 failures.

    • 0.spi_device_intercept.79619990960167922700332090869831317973520701520034821010214791857703719959398
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest/run.log

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