b7bab30| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 24.950s | 5.213ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | sram_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| sram_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | mem_walk | sram_ctrl_mem_walk | 3.668m | 21.594ms | 1 | 1 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 1.783m | 20.931ms | 1 | 1 | 100.00 |
| V1 | TOTAL | 3 | 8 | 37.50 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 8.118m | 16.672ms | 1 | 1 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 2.481m | 8.228ms | 1 | 1 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 6.158m | 8.576ms | 1 | 1 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 18.649s | 0 | 1 | 0.00 | |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 49.650s | 50.557ms | 1 | 1 | 100.00 |
| V2 | executable | sram_ctrl_executable | 4.174m | 5.942ms | 1 | 1 | 100.00 |
| V2 | partial_access | sram_ctrl_partial_access | 10.910s | 4.400ms | 1 | 1 | 100.00 |
| sram_ctrl_partial_access_b2b | 4.612m | 72.452ms | 1 | 1 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 16.248s | 0 | 1 | 0.00 | |
| sram_ctrl_throughput_w_partial_write | 11.430s | 3.575ms | 1 | 1 | 100.00 | ||
| sram_ctrl_throughput_w_readback | 18.480s | 920.510us | 1 | 1 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 4.310m | 17.670ms | 1 | 1 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 2.360s | 1.348ms | 1 | 1 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 1.338h | 340.328ms | 1 | 1 | 100.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.600s | 65.242us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| sram_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| sram_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| sram_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| sram_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| sram_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| sram_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 13 | 17 | 76.47 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | tl_intg_err | sram_ctrl_sec_cm | 0.590s | 2.228us | 0 | 1 | 0.00 |
| sram_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | prim_count_check | sram_ctrl_sec_cm | 0.590s | 2.228us | 0 | 1 | 0.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 4.310m | 17.670ms | 1 | 1 | 100.00 |
| V2S | sec_cm_readback_config_regwen | sram_ctrl_regwen | 4.310m | 17.670ms | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 4.174m | 5.942ms | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 4.174m | 5.942ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 4.174m | 5.942ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 49.650s | 50.557ms | 1 | 1 | 100.00 |
| V2S | sec_cm_prim_ram_ctrl_mubi | sram_ctrl_mubi_enc_err | 3.740s | 2.665ms | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_mem_readback | sram_ctrl_readback_err | 3.730s | 9.476ms | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 24.950s | 5.213ms | 1 | 1 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 24.950s | 5.213ms | 1 | 1 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 4.174m | 5.942ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0.590s | 2.228us | 0 | 1 | 0.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 49.650s | 50.557ms | 1 | 1 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0.590s | 2.228us | 0 | 1 | 0.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0.590s | 2.228us | 0 | 1 | 0.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 24.950s | 5.213ms | 1 | 1 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0.590s | 2.228us | 0 | 1 | 0.00 |
| V2S | TOTAL | 2 | 5 | 40.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 59.220s | 7.539ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 19 | 31 | 61.29 |
Job killed most likely because its dependent job failed. has 9 failures:
Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
Test sram_ctrl_tl_errors has 1 failures.
Test sram_ctrl_tl_intg_err has 1 failures.
Test sram_ctrl_csr_hw_reset has 1 failures.
Test sram_ctrl_csr_rw has 1 failures.
... and 4 more tests.
Job returned non-zero exit code has 3 failures:
Test cover_reg_top has 1 failures.
cover_reg_top
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/cover_reg_top/build.log
recompiling module sram_ctrl_cov_bind
All of 106 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
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CPU time: 15.903 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Test sram_ctrl_max_throughput has 1 failures.
0.sram_ctrl_max_throughput.9247308326058095952451026734735225204557011501122043530431874653728751768820
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:35 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test sram_ctrl_access_during_key_req has 1 failures.
0.sram_ctrl_access_during_key_req.4229728739613839252897933057970662377749608373765325328163478262192716354732
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:35 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Offending '(!$isunknown(rdata_o))' has 1 failures:
0.sram_ctrl_sec_cm.15173162717932545200610319880648762041464186467615965752906984937262289951637
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 2227615 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2227615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---