b7bab30| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 11.170s | 17.084ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 18.304s | 0 | 1 | 0.00 | |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.640s | 16.446us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 1.350s | 46.037us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.700s | 17.763us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 0.920s | 115.431us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.640s | 16.446us | 1 | 1 | 100.00 |
| sram_ctrl_csr_aliasing | 0.700s | 17.763us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 3.780s | 443.155us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 3.240s | 340.713us | 1 | 1 | 100.00 |
| V1 | TOTAL | 6 | 8 | 75.00 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 4.615m | 2.959ms | 1 | 1 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 1.401m | 1.305ms | 1 | 1 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 53.730s | 5.823ms | 1 | 1 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 6.107m | 46.747ms | 1 | 1 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 3.260s | 298.480us | 1 | 1 | 100.00 |
| V2 | executable | sram_ctrl_executable | 1.400m | 4.129ms | 1 | 1 | 100.00 |
| V2 | partial_access | sram_ctrl_partial_access | 7.290s | 665.116us | 1 | 1 | 100.00 |
| sram_ctrl_partial_access_b2b | 4.275m | 58.185ms | 1 | 1 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 25.680s | 125.247us | 1 | 1 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 36.090s | 155.811us | 1 | 1 | 100.00 | ||
| sram_ctrl_throughput_w_readback | 20.197s | 0 | 1 | 0.00 | |||
| V2 | regwen | sram_ctrl_regwen | 7.725m | 3.215ms | 1 | 1 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.700s | 43.568us | 1 | 1 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 8.061m | 25.539ms | 1 | 1 | 100.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.620s | 173.320us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 1.790s | 44.410us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 1.790s | 44.410us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 18.304s | 0 | 1 | 0.00 | |
| sram_ctrl_csr_rw | 0.640s | 16.446us | 1 | 1 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.700s | 17.763us | 1 | 1 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.770s | 76.868us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 18.304s | 0 | 1 | 0.00 | |
| sram_ctrl_csr_rw | 0.640s | 16.446us | 1 | 1 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.700s | 17.763us | 1 | 1 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.770s | 76.868us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 16 | 17 | 94.12 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 2.380s | 497.001us | 1 | 1 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 0.720s | 23.518us | 0 | 1 | 0.00 |
| sram_ctrl_tl_intg_err | 1.120s | 92.999us | 1 | 1 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 0.720s | 23.518us | 0 | 1 | 0.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 1.120s | 92.999us | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 7.725m | 3.215ms | 1 | 1 | 100.00 |
| V2S | sec_cm_readback_config_regwen | sram_ctrl_regwen | 7.725m | 3.215ms | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.640s | 16.446us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 1.400m | 4.129ms | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 1.400m | 4.129ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 1.400m | 4.129ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 3.260s | 298.480us | 1 | 1 | 100.00 |
| V2S | sec_cm_prim_ram_ctrl_mubi | sram_ctrl_mubi_enc_err | 0.820s | 134.477us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 2.380s | 497.001us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_readback_err | 0.770s | 26.039us | 0 | 1 | 0.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 11.170s | 17.084ms | 1 | 1 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 11.170s | 17.084ms | 1 | 1 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 1.400m | 4.129ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0.720s | 23.518us | 0 | 1 | 0.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 3.260s | 298.480us | 1 | 1 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0.720s | 23.518us | 0 | 1 | 0.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0.720s | 23.518us | 0 | 1 | 0.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 11.170s | 17.084ms | 1 | 1 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0.720s | 23.518us | 0 | 1 | 0.00 |
| V2S | TOTAL | 3 | 5 | 60.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 1.521m | 6.857ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 26 | 31 | 83.87 |
Job returned non-zero exit code has 2 failures:
Test sram_ctrl_throughput_w_readback has 1 failures.
0.sram_ctrl_throughput_w_readback.42636658299040463717287650117732565065166550572314035059083811706399487859572
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_readback/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:26 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test sram_ctrl_csr_hw_reset has 1 failures.
0.sram_ctrl_csr_hw_reset.26828789602157498455030053432215386041168685891737407041087608032765656705676
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 19:26 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
0.sram_ctrl_readback_err.24223256400493809159342509524983983516823976697770907053987202648189358117727
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 26038708 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x18) != exp (0x66)
UVM_INFO @ 26038708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
0.sram_ctrl_sec_cm.112694396095845615131425603761779577902425287439365361068068119346237966479151
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 23518118 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 23518118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
0.sram_ctrl_csr_mem_rw_with_rand_reset.91687881096778031575232439152669107899958525428644037520896335084775249248495
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 115430972 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 115430972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---