SYSRST_CTRL Simulation Results

Monday September 22 2025 19:22:52 UTC

GitHub Revision: b7bab30

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.290s 2.114ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 24.048s 0 1 0.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 4.650s 2.236ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.350s 2.324ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 3.000s 6.074ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.560s 2.088ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 9.960s 15.709ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.650s 3.081ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.560s 2.088ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.650s 3.081ms 1 1 100.00
V1 TOTAL 7 9 77.78
V2 combo_detect sysrst_ctrl_combo_detect 1.041m 150.927ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 24.670s 26.837ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 1.980s 3.268ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 4.930s 3.218ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 4.610s 2.508ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 20.241s 0 1 0.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 2.110s 4.446ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 3.100s 2.613ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 1.620s 8.996ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 11.620s 33.819ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 22.700s 15.802ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.370s 2.013ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 1.220s 2.026ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 4.810s 2.046ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 4.810s 2.046ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 3.000s 6.074ms 1 1 100.00
sysrst_ctrl_csr_rw 2.560s 2.088ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.650s 3.081ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.170s 9.983ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 3.000s 6.074ms 1 1 100.00
sysrst_ctrl_csr_rw 2.560s 2.088ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.650s 3.081ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.170s 9.983ms 1 1 100.00
V2 TOTAL 14 15 93.33
V2S tl_intg_err sysrst_ctrl_sec_cm 1.153m 42.012ms 1 1 100.00
sysrst_ctrl_tl_intg_err 1.170m 42.719ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.170m 42.719ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 14.290s 7.106ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 24 27 88.89

Failure Buckets