UART Simulation Results

Monday September 22 2025 19:22:52 UTC

GitHub Revision: b7bab30

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	0.910s	275.465us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.580s	28.964us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.590s	27.155us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.700s	59.775us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.700s	33.462us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.680s	41.223us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.590s	27.155us	1	1	100.00
		uart_csr_aliasing	0.700s	33.462us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	9.000s	35.522ms	1	1	100.00
V2	parity	uart_smoke	0.910s	275.465us	1	1	100.00
		uart_tx_rx	9.000s	35.522ms	1	1	100.00
V2	parity_error	uart_intr	17.560s	25.045ms	1	1	100.00
		uart_rx_parity_err	25.230s	35.766ms	1	1	100.00
V2	watermark	uart_tx_rx	9.000s	35.522ms	1	1	100.00
		uart_intr	17.560s	25.045ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.174m	119.169ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	12.380s	84.367ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.380m	119.483ms	1	1	100.00
V2	rx_frame_err	uart_intr	17.560s	25.045ms	1	1	100.00
V2	rx_break_err	uart_intr	17.560s	25.045ms	1	1	100.00
V2	rx_timeout	uart_intr	17.560s	25.045ms	1	1	100.00
V2	perf	uart_perf	18.020s		0	1	0.00
V2	sys_loopback	uart_loopback	6.360s	4.789ms	1	1	100.00
V2	line_loopback	uart_loopback	6.360s	4.789ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	5.550s	17.148ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	6.510s	40.947ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.850s	1.301ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	10.210s	6.809ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	8.226m	166.545ms	1	1	100.00
V2	stress_all	uart_stress_all	6.000s	10.116ms	0	1	0.00
V2	alert_test	uart_alert_test	0.550s	14.147us	1	1	100.00
V2	intr_test	uart_intr_test	0.560s	155.511us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.070s	103.565us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.070s	103.565us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.580s	28.964us	1	1	100.00
		uart_csr_rw	0.590s	27.155us	1	1	100.00
		uart_csr_aliasing	0.700s	33.462us	1	1	100.00
		uart_same_csr_outstanding	0.610s	230.160us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.580s	28.964us	1	1	100.00
		uart_csr_rw	0.590s	27.155us	1	1	100.00
		uart_csr_aliasing	0.700s	33.462us	1	1	100.00
		uart_same_csr_outstanding	0.610s	230.160us	1	1	100.00
V2		TOTAL			15	18	83.33
V2S	tl_intg_err	uart_sec_cm	0.750s	163.096us	1	1	100.00
		uart_tl_intg_err	1.150s	180.184us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.150s	180.184us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.630s	2.092ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			23	27	85.19

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 3 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.73410358780566229568729076698023816743641574370307525222643913112292971951807
      Line 77, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 12694671745 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 13143605922 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 13143640405 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 13143950752 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (53 [0x35] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 13143985235 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
      

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.94548184025017563905535094632942574679040297450802878587424138417470352547959
      Line 101, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1093769128 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1095665022 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1099519312 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1102696497 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1110884259 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.99054712465530914709291888346489467661181778164561645115254618541954684409055
      Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 1742385664 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1742385664 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 3185149632 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3185149632 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 3214435112 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (36 [0x24] vs 171 [0xab]) reg name: uart_reg_block.rdata
      

• Job returned non-zero exit code has 1 failures:

  • Test uart_perf has 1 failures.

    • 0.uart_perf.34561598434571824375861209251341369969562080362802163186372050961822583082340
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_perf/latest/run.log

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        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255