CHIP Simulation Results

Monday September 22 2025 19:22:52 UTC

GitHub Revision: b7bab30

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	9.842s		0	1	0.00
		chip_sw_example_rom	18.339s		0	1	0.00
		chip_sw_example_manufacturer	17.365s		0	1	0.00
		chip_sw_example_concurrency	15.124s		0	1	0.00
V1	csr_hw_reset	chip_csr_hw_reset	2.645m	5.092ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.849m	4.288ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.747m	7.271ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	37.010m	33.826ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	38.830s	2.582ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	37.010m	33.826ms	1	1	100.00
		chip_csr_rw	2.849m	4.288ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	4.150s	43.246us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.625s		0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.625s		0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.625s		0	1	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	13.582s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	13.582s		0	1	0.00
		chip_sw_uart_tx_rx_idx1	13.003s		0	1	0.00
		chip_sw_uart_tx_rx_idx2	13.203s		0	1	0.00
		chip_sw_uart_tx_rx_idx3	10.782s		0	1	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	14.035s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	13.716s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	9.621s		0	1	0.00
V1		TOTAL			5	18	27.78
V2	chip_pin_mux	chip_padctrl_attributes	23.427s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	23.427s		0	1	0.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	9.488s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.441s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	19.250s		0	1	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	18.595s		0	1	0.00
		chip_tap_straps_testunlock0	15.306s		0	1	0.00
		chip_tap_straps_rma	22.574s		0	1	0.00
		chip_tap_straps_prod	11.757s		0	1	0.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	12.857s		0	1	0.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	15.542s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	9.428s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	9.428s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	22.483s		0	1	0.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	16.683s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	9.479s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	9.943s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	24.028s		0	1	0.00
		chip_sw_aes_enc_jitter_en	18.897s		0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	10.597s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	14.521s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	22.170s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.723s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	37.005s		0	1	0.00
		chip_sw_clkmgr_jitter	18.068s		0	1	0.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	10.243s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	27.980s		0	1	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	18.967s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	14.043s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	18.967s		0	1	0.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	17.577s		0	1	0.00
		chip_sw_aes_smoketest	17.289s		0	1	0.00
		chip_sw_aon_timer_smoketest	15.642s		0	1	0.00
		chip_sw_clkmgr_smoketest	16.046s		0	1	0.00
		chip_sw_csrng_smoketest	16.658s		0	1	0.00
		chip_sw_entropy_src_smoketest	14.653s		0	1	0.00
		chip_sw_gpio_smoketest	15.879s		0	1	0.00
		chip_sw_hmac_smoketest	14.133s		0	1	0.00
		chip_sw_kmac_smoketest	16.283s		0	1	0.00
		chip_sw_otbn_smoketest	15.249s		0	1	0.00
		chip_sw_pwrmgr_smoketest	14.010s		0	1	0.00
		chip_sw_pwrmgr_usbdev_smoketest	14.515s		0	1	0.00
		chip_sw_rv_plic_smoketest	14.050s		0	1	0.00
		chip_sw_rv_timer_smoketest	12.806s		0	1	0.00
		chip_sw_rstmgr_smoketest	15.906s		0	1	0.00
		chip_sw_sram_ctrl_smoketest	21.722s		0	1	0.00
		chip_sw_uart_smoketest	21.562s		0	1	0.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	15.553s		0	1	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	16.985s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	9.773s		0	1	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	15.374s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	16.582s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	16.678s		0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	17.313s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	9.564s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	13.985s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	41.080s	2.877ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	41.080s	2.877ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	37.010m	33.826ms	1	1	100.00
		chip_same_csr_outstanding	25.385s		0	1	0.00
		chip_csr_hw_reset	2.645m	5.092ms	1	1	100.00
		chip_csr_rw	2.849m	4.288ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	37.010m	33.826ms	1	1	100.00
		chip_same_csr_outstanding	25.385s		0	1	0.00
		chip_csr_hw_reset	2.645m	5.092ms	1	1	100.00
		chip_csr_rw	2.849m	4.288ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	34.680s	1.904ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	3.870s	42.846us	1	1	100.00
		xbar_smoke_large_delays			0	1	0.00
		xbar_smoke_slow_rsp	29.930s	3.859ms	1	1	100.00
		xbar_random_zero_delays	26.240s	617.932us	1	1	100.00
		xbar_random_large_delays	3.246m	36.035ms	1	1	100.00
		xbar_random_slow_rsp	3.131m	24.947ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	27.695s		0	1	0.00
		xbar_error_and_unmapped_addr	15.460s	739.840us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	17.330s	376.079us	1	1	100.00
		xbar_error_and_unmapped_addr	15.460s	739.840us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	27.460s	1.328ms	1	1	100.00
		xbar_access_same_device_slow_rsp	33.030s	4.122ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	16.040s	983.587us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.734m	5.424ms	1	1	100.00
		xbar_stress_all_with_error	12.960s	270.490us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	21.940s	104.818us	1	1	100.00
		xbar_stress_all_with_reset_error	2.658m	6.933ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	15.374s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	15.776s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	15.552s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	15.460s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.686s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.646s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.979s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.492s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.591s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.175s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.286s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.504s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.133s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.180s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.984s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.027s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.080s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.984s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.286s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.829s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.759s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	14.236s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.081s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.728s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	14.035s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.488s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	14.052s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.525s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.516s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	19.714s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.600s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.126s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.029s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	18.606s		0	1	0.00
		rom_e2e_asm_init_dev	17.128s		0	1	0.00
		rom_e2e_asm_init_prod	16.125s		0	1	0.00
		rom_e2e_asm_init_prod_end	15.254s		0	1	0.00
		rom_e2e_asm_init_rma	16.126s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	15.005s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	15.481s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	16.004s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	16.165s		0	1	0.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	18.140s		0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	18.140s		0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	23.921s		0	1	0.00
		chip_sw_aes_enc_jitter_en	18.897s		0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	14.130s		0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	10.642s		0	1	0.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	36.530s		0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	19.042s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.688s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	9.496s		0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	13.985s		0	1	0.00
		chip_plic_all_irqs_10	21.068s		0	1	0.00
		chip_plic_all_irqs_20	9.886s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	16.058s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	19.284s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.775s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.041s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.580s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.872s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.468s		0	1	0.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	9.724s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9.989s		0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	9.602s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	14.010s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	9.602s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	19.517s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	19.517s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.504s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	29.404s		0	1	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	25.060s		0	1	0.00
		chip_sw_aes_idle	10.642s		0	1	0.00
		chip_sw_hmac_enc_idle	37.768s		0	1	0.00
		chip_sw_kmac_idle	21.956s		0	1	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.292s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.627s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.312s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.085s		0	1	0.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	13.101s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.153s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	9.787s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.149s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.876s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.093s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.191s		0	1	0.00
		chip_sw_ast_clk_outputs	22.483s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.768s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.149s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.876s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	9.479s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	9.943s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	24.028s		0	1	0.00
		chip_sw_aes_enc_jitter_en	18.897s		0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	10.597s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	14.521s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	22.170s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.723s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	37.005s		0	1	0.00
		chip_sw_clkmgr_jitter	18.068s		0	1	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	9.735s		0	1	0.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	9.632s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.733s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	9.637s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	9.792s		0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	9.637s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.685s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	16.125s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	18.263s		0	1	0.00
		chip_sw_flash_init_reduced_freq	18.940s		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	18.573s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	22.483s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	21.309s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.343s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	9.496s		0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.872s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.957s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.451s		0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	14.240s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	14.455s		0	1	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.648s		0	1	0.00
		chip_sw_entropy_src_ast_rng_req	13.975s		0	1	0.00
		chip_sw_edn_entropy_reqs	14.458s		0	1	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	13.975s		0	1	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.957s		0	1	0.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	15.475s		0	1	0.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.536s		0	1	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.730s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	9.943s		0	1	0.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	9.633s		0	1	0.00
		chip_sw_flash_ctrl_ops_jitter_en	9.479s		0	1	0.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	17.744s		0	1	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.536s		0	1	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	9.678s		0	1	0.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	18.175s		0	1	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.678s		0	1	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	17.744s		0	1	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.678s		0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.678s		0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	9.678s		0	1	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.678s		0	1	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	9.496s		0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.106m	9.120ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	16.232s		0	1	0.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	10.088s		0	1	0.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	10.088s		0	1	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	9.452s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	14.521s		0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	37.768s		0	1	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	37.124s		0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	41.678s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	9.469s		0	1	0.00
		chip_sw_i2c_host_tx_rx_idx1	9.683s		0	1	0.00
		chip_sw_i2c_host_tx_rx_idx2	9.582s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.591s		0	1	0.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	18.175s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	22.170s		0	1	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.434s		0	1	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	36.530s		0	1	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	22.486s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	22.004s		0	1	0.00
		chip_sw_kmac_mode_kmac	41.133s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.723s		0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	18.175s		0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.257s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	21.846s		0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	13.570s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	21.956s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.688s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	18.595s		0	1	0.00
		chip_tap_straps_rma	22.574s		0	1	0.00
		chip_tap_straps_prod	11.757s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	13.794s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.257s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.257s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.257s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	41.889s		0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	9.678s		0	1	0.00
		chip_sw_flash_rma_unlocked	17.744s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.055s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.590s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	9.790s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	9.522s		0	1	0.00
		chip_sw_lc_ctrl_transition	21.257s		0	1	0.00
		chip_sw_keymgr_key_derivation	18.175s		0	1	0.00
		chip_sw_rom_ctrl_integrity_check	26.819s		0	1	0.00
		chip_sw_sram_ctrl_execution_main	16.036s		0	1	0.00
		chip_prim_tl_access	3.106m	9.120ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.768s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.153s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	9.787s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.149s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.876s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.093s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.191s		0	1	0.00
		chip_tap_straps_dev	18.595s		0	1	0.00
		chip_tap_straps_rma	22.574s		0	1	0.00
		chip_tap_straps_prod	11.757s		0	1	0.00
		chip_rv_dm_lc_disabled	42.300s	2.380ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	21.528s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	21.747s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	20.943s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	12.254s		0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	14.267s		0	1	0.00
		chip_rv_dm_lc_disabled	42.300s	2.380ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	20.202s		0	1	0.00
		chip_sw_lc_walkthrough_prod	20.369s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	16.921s		0	1	0.00
		chip_sw_lc_walkthrough_rma	9.487s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	14.267s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	16.063s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	9.490s		0	1	0.00
		rom_volatile_raw_unlock	16.632s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	24.296s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	24.028s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	25.060s		0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	25.060s		0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	25.060s		0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	25.305s		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.257s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.536s		0	1	0.00
		chip_sw_otbn_mem_scramble	25.305s		0	1	0.00
		chip_sw_keymgr_key_derivation	18.175s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	17.951s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	11.224s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.536s		0	1	0.00
		chip_sw_otbn_mem_scramble	25.305s		0	1	0.00
		chip_sw_keymgr_key_derivation	18.175s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	17.951s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	11.224s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.257s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	18.990s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	13.794s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.055s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.590s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	9.790s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	9.522s		0	1	0.00
		chip_sw_lc_ctrl_transition	21.257s		0	1	0.00
		chip_prim_tl_access	3.106m	9.120ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.106m	9.120ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	13.862s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	13.988s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	27.679s		0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	22.734s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	9.473s		0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	13.705s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	21.188s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	17.849s		0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	19.517s		0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	18.540s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	28.864s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	13.988s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	18.911s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	9.733s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.577s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	13.602s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.112s		0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.431s		0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs	19.014s		0	1	0.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	18.593s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	9.519s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	9.496s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	26.819s		0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	26.819s		0	1	0.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	19.014s		0	1	0.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.112s		0	1	0.00
		chip_sw_pwrmgr_wdog_reset	28.864s		0	1	0.00
		chip_sw_pwrmgr_smoketest	14.010s		0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	27.107s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	18.378s		0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	19.076s		0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	19.284s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	19.124s		0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	9.496s		0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.468s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	24.137s		0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	14.897s		0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	11.152s		0	1	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	11.224s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	18.378s		0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	18.378s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	37.978s		0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	9.680m	13.862ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	27.107s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	15.828s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	16.599s		0	1	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	22.574s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	42.300s	2.380ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	13.985s		0	1	0.00
		chip_plic_all_irqs_10	21.068s		0	1	0.00
		chip_plic_all_irqs_20	9.886s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	14.145s		0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	13.827s		0	1	0.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	15.374s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.593s		0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.997s		0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	9.641s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	9.642s		0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	17.951s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	37.005s		0	1	0.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	19.006s		0	1	0.00
		chip_sw_sleep_sram_ret_contents_scramble	26.531s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.036s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	9.496s		0	1	0.00
		chip_sw_data_integrity_escalation	9.428s		0	1	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.431s		0	1	0.00
		chip_sw_sysrst_ctrl_reset	13.406s		0	1	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	14.091s		0	1	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	12.304s		0	1	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	14.200s		0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	13.406s		0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	13.406s		0	1	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	9.552s		0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	9.552s		0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	13.773s		0	1	0.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	18.140s		0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	9.672s		0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	13.572s		0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	13.420s		0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	13.478s		0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	13.058s		0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	9.622s		0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	13.673s		0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	9.622s		0	1	0.00
V2		TOTAL			17	275	6.18
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	20.321s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	10.591s		0	1	0.00
V2S		TOTAL			0	2	0.00
V3	chip_sw_coremark	chip_sw_coremark	19.235s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.105s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.818s		0	1	0.00
		rom_e2e_jtag_debug_dev	17.440s		0	1	0.00
		rom_e2e_jtag_debug_rma	17.072s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	16.119s		0	1	0.00
		rom_e2e_jtag_inject_dev	15.691s		0	1	0.00
		rom_e2e_jtag_inject_rma	15.006s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.293s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.739s		0	1	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	14.184s		0	1	0.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.611s		0	1	0.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.128s		0	1	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	14.563s		0	1	0.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	18.814s		0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	9.774s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.564s		0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	26.206s		0	1	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.630s		0	1	0.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	19.014s		0	1	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.818s		0	1	0.00
		rom_e2e_jtag_debug_dev	17.440s		0	1	0.00
		rom_e2e_jtag_debug_rma	17.072s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	26.164s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	9.496s		0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	13.726s		0	1	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	13.726s		0	1	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	13.694s		0	1	0.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	13.582s		0	1	0.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	9.825s		0	1	0.00
V3		TOTAL			0	23	0.00
	Unmapped tests	chip_sival_flash_info_access	11.065s		0	1	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	9.544s		0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	22.111s		0	1	0.00
		chip_sw_otp_ctrl_descrambling	22.012s		0	1	0.00
		chip_sw_pwrmgr_lowpower_cancel	19.293s		0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	20.058s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	9.787s		0	1	0.00
		TOTAL			22	325	6.77

Failure Buckets

• Job returned non-zero exit code has 299 failures:

  • Test chip_same_csr_outstanding has 1 failures.

    • 0.chip_same_csr_outstanding.111939792297955921070882283620025508633110121895478104362733826843346040872572
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 19:47 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test chip_sw_example_flash has 1 failures.

    • 0.chip_sw_example_flash.112227112713175437183222595960781165385523245590430595419238968473069782859001
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log

                    done; \
                fi; \
            fi; \
        done;
        Building SW image "//sw/device/tests:example_test_from_flash_sim_dv".
        Building "//sw/device/tests:example_test_from_flash_sim_dv" on network connected machine.
        Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_test_from_flash_sim_dv
        Computing main repo mapping:
        ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/bazel_skylib/1.7.1/MODULE.bazel: Unknown host: bcr.bazel.build
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32
      

  • Test chip_sw_example_rom has 1 failures.

    • 0.chip_sw_example_rom.34110795509735655998679685523099649355674437233546299684765994232500650495942
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_rust+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp428471016282775530/rules_rust-0.59.2.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: @rules_rust//rust/toolchain/channel :: Error loading option @rules_rust//rust/toolchain/channel: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp428471016282775530/rules_rust-0.59.2.tar.gz: Unknown host: release-assets.githubusercontent.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 2
      

  • Test chip_sw_example_manufacturer has 1 failures.

    • 0.chip_sw_example_manufacturer.4992563124872210414967666508262088025513970556672981160073367580098894035455
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_rust+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp8423130847952788662/rules_rust-0.59.2.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: @rules_rust//rust/toolchain/channel :: Error loading option @rules_rust//rust/toolchain/channel: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp8423130847952788662/rules_rust-0.59.2.tar.gz: Unknown host: release-assets.githubusercontent.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 2
      

  • Test chip_sw_example_concurrency has 1 failures.

    • 0.chip_sw_example_concurrency.76334220047384061255769589610958119628713196160974998720202919577574315478434
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_rust+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp3581871793698477345/rules_rust-0.59.2.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: @rules_rust//rust/toolchain/channel :: Error loading option @rules_rust//rust/toolchain/channel: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp3581871793698477345/rules_rust-0.59.2.tar.gz: Unknown host: release-assets.githubusercontent.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 2
      

  • ... and 294 more tests.

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34800) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.71594293382589001364689452333783118040631580830693769084877957321664819616161
      Line 224, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

        UVM_ERROR @ 2876.729730 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34800) { a_addr: 'h10410  a_data: 'ha3b8e3f6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h4  a_user: 'h1b14d  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2876.729730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:

  • Test chip_rv_dm_lc_disabled has 1 failures.

    • 0.chip_rv_dm_lc_disabled.31918899048408517314421117186604064944556501731273672987732983600733669071187
      Line 198, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

        UVM_ERROR @ 2379.535359 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105f0 read out mismatch
        UVM_INFO @ 2379.535359 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test xbar_smoke_large_delays has 1 failures.

    • 0.xbar_smoke_large_delays.86197690137261425258763562911857939444264674391317717929733893470078364570479
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32594) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.chip_csr_mem_rw_with_rand_reset.5557311460034154439913579473436354644888006842080466032851641949801531943873
      Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2581.904514 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32594) { a_addr: 'h106e0  a_data: 'h65febf38  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h19e7d  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2581.904514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---