ff105ef| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 3.170s | 5.958ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 1.160s | 1.344ms | 1 | 1 | 100.00 |
| V1 | csr_rw | adc_ctrl_csr_rw | 0.800s | 389.624us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 18.125s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 1.420s | 827.514us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 1.060s | 499.641us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 0.800s | 389.624us | 1 | 1 | 100.00 |
| adc_ctrl_csr_aliasing | 1.420s | 827.514us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 7.573m | 336.636ms | 1 | 1 | 100.00 |
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 4.098m | 333.373ms | 1 | 1 | 100.00 |
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 8.833m | 330.440ms | 1 | 1 | 100.00 |
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 1.101m | 164.312ms | 1 | 1 | 100.00 |
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 2.452m | 354.855ms | 1 | 1 | 100.00 |
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 4.014m | 621.308ms | 1 | 1 | 100.00 |
| V2 | filters_both | adc_ctrl_filters_both | 3.917m | 595.863ms | 1 | 1 | 100.00 |
| V2 | clock_gating | adc_ctrl_clock_gating | 6.080m | 2.000s | 0 | 1 | 0.00 |
| V2 | poweron_counter | adc_ctrl_poweron_counter | 8.850s | 4.806ms | 1 | 1 | 100.00 |
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 15.580s | 36.799ms | 1 | 1 | 100.00 |
| V2 | fsm_reset | adc_ctrl_fsm_reset | 58.390s | 80.092ms | 1 | 1 | 100.00 |
| V2 | stress_all | adc_ctrl_stress_all | 10.887m | 424.231ms | 1 | 1 | 100.00 |
| V2 | alert_test | adc_ctrl_alert_test | 0.700s | 413.341us | 1 | 1 | 100.00 |
| V2 | intr_test | adc_ctrl_intr_test | 1.030s | 407.370us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 1.850s | 503.903us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 1.850s | 503.903us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 1.160s | 1.344ms | 1 | 1 | 100.00 |
| adc_ctrl_csr_rw | 0.800s | 389.624us | 1 | 1 | 100.00 | ||
| adc_ctrl_csr_aliasing | 1.420s | 827.514us | 1 | 1 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 7.860s | 4.379ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 1.160s | 1.344ms | 1 | 1 | 100.00 |
| adc_ctrl_csr_rw | 0.800s | 389.624us | 1 | 1 | 100.00 | ||
| adc_ctrl_csr_aliasing | 1.420s | 827.514us | 1 | 1 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 7.860s | 4.379ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 15 | 16 | 93.75 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 24.932s | 0 | 1 | 0.00 | |
| adc_ctrl_tl_intg_err | 5.610s | 8.838ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 5.610s | 8.838ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 34.750s | 1.977s | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 21 | 25 | 84.00 |
Job returned non-zero exit code has 2 failures:
Test adc_ctrl_sec_cm has 1 failures.
0.adc_ctrl_sec_cm.80143345648716842803246988407013650509362322714602204946853627203987333039887
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 23 18:51 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test adc_ctrl_csr_bit_bash has 1 failures.
0.adc_ctrl_csr_bit_bash.103640959345495195356636161711722450356268448172989755904274966911481801360885
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 23 18:49 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
0.adc_ctrl_clock_gating.72039421979887053712446588394818262615201994198277210721486790897450743597586
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
0.adc_ctrl_stress_all_with_rand_reset.99052141474535473900154558120285610940516600709281877600620799715974669361988
Line 215, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1976856304871 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1976856304871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---