ff105ef| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 30.000s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 21.000s | 0 | 1 | 0.00 | |
| V1 | csr_rw | csrng_csr_rw | 46.000s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 33.000s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | csrng_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 25.000s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 46.000s | 0 | 1 | 0.00 | |
| csrng_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |||
| V1 | TOTAL | 0 | 6 | 0.00 | |||
| V2 | interrupts | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| V2 | alerts | csrng_alert | 18.000s | 0 | 1 | 0.00 | |
| V2 | err | csrng_err | 30.000s | 0 | 1 | 0.00 | |
| V2 | cmds | csrng_cmds | 18.000s | 0 | 1 | 0.00 | |
| V2 | life cycle | csrng_cmds | 18.000s | 0 | 1 | 0.00 | |
| V2 | stress_all | csrng_stress_all | 29.000s | 0 | 1 | 0.00 | |
| V2 | intr_test | csrng_intr_test | 22.000s | 0 | 1 | 0.00 | |
| V2 | alert_test | csrng_alert_test | 38.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 21.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_illegal_access | csrng_tl_errors | 21.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 21.000s | 0 | 1 | 0.00 | |
| csrng_csr_rw | 46.000s | 0 | 1 | 0.00 | |||
| csrng_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |||
| csrng_same_csr_outstanding | 21.000s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 21.000s | 0 | 1 | 0.00 | |
| csrng_csr_rw | 46.000s | 0 | 1 | 0.00 | |||
| csrng_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |||
| csrng_same_csr_outstanding | 21.000s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 0 | 9 | 0.00 | |||
| V2S | tl_intg_err | csrng_sec_cm | 11.000s | 0 | 1 | 0.00 | |
| csrng_tl_intg_err | 21.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_config_regwen | csrng_regwen | 33.000s | 0 | 1 | 0.00 | |
| csrng_csr_rw | 46.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_config_mubi | csrng_alert | 18.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 11.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 11.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 11.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 11.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 11.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 11.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 11.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 18.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 18.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 21.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 11.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 11.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 38.000s | 0 | 1 | 0.00 | |
| csrng_err | 30.000s | 0 | 1 | 0.00 | |||
| V2S | TOTAL | 0 | 3 | 0.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 13.000s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 0 | 19 | 0.00 |
Job returned non-zero exit code has 19 failures:
Test csrng_smoke has 1 failures.
0.csrng_smoke.32720494464268015424764029333466336107890615299930471145738607857880340998333
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 23, 2025 at 18:48:20 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_cmds has 1 failures.
0.csrng_cmds.14882000753135458317078561641680280819629577938321823453755810385960072799555
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_cmds/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 23, 2025 at 18:48:09 UTC (total: 00:00:18)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_stress_all has 1 failures.
0.csrng_stress_all.40741126088495638870488339407571385843955345828911086980485140980801746698147
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 23, 2025 at 18:48:21 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_intr has 1 failures.
0.csrng_intr.4268815263810580714101424883323834544797554415531455253309428035688841658366
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 23, 2025 at 18:48:30 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_alert has 1 failures.
0.csrng_alert.39832314675688017741997593066026368757999360388158964176330335193692855776982
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 23, 2025 at 18:48:10 UTC (total: 00:00:18)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 14 more tests.