EDN Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.800s	51.422us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.770s	20.242us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.770s	26.254us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.180s	218.481us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.850s	49.804us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.130s	203.189us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.770s	26.254us	1	1	100.00
		edn_csr_aliasing	0.850s	49.804us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.020s	218.636us	1	1	100.00
V2	csrng_commands	edn_genbits	2.020s	218.636us	1	1	100.00
V2	genbits	edn_genbits	2.020s	218.636us	1	1	100.00
V2	interrupts	edn_intr	0.730s	52.589us	1	1	100.00
V2	alerts	edn_alert	0.960s	50.090us	1	1	100.00
V2	errs	edn_err	0.810s	19.344us	1	1	100.00
V2	disable	edn_disable	0.730s	16.460us	1	1	100.00
		edn_disable_auto_req_mode	0.870s	55.524us	1	1	100.00
V2	stress_all	edn_stress_all	2.830s	954.807us	1	1	100.00
V2	intr_test	edn_intr_test	0.730s	12.953us	1	1	100.00
V2	alert_test	edn_alert_test	0.730s	25.593us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.490s	205.835us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.490s	205.835us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.770s	20.242us	1	1	100.00
		edn_csr_rw	0.770s	26.254us	1	1	100.00
		edn_csr_aliasing	0.850s	49.804us	1	1	100.00
		edn_same_csr_outstanding	0.860s	35.937us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.770s	20.242us	1	1	100.00
		edn_csr_rw	0.770s	26.254us	1	1	100.00
		edn_csr_aliasing	0.850s	49.804us	1	1	100.00
		edn_same_csr_outstanding	0.860s	35.937us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.700s	608.615us	1	1	100.00
		edn_tl_intg_err	1.970s	109.849us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.750s	38.891us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.960s	50.090us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.700s	608.615us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.700s	608.615us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.700s	608.615us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.700s	608.615us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.960s	50.090us	1	1	100.00
		edn_sec_cm	3.700s	608.615us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.960s	50.090us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.970s	109.849us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	15.390s	7.133ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00