HMAC Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.520s 197.228us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.810s 64.530us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.670s 42.703us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.070s 2.318ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.340s 315.490us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.050s 28.362us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.670s 42.703us 1 1 100.00
hmac_csr_aliasing 2.340s 315.490us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 59.960s 3.439ms 1 1 100.00
V2 back_pressure hmac_back_pressure 18.660s 1.705ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.714m 5.128ms 1 1 100.00
hmac_test_sha384_vectors 5.924m 22.888ms 1 1 100.00
hmac_test_sha512_vectors 18.850s 504.911us 1 1 100.00
hmac_test_hmac256_vectors 5.380s 197.036us 1 1 100.00
hmac_test_hmac384_vectors 6.640s 1.839ms 1 1 100.00
hmac_test_hmac512_vectors 9.000s 317.368us 1 1 100.00
V2 burst_wr hmac_burst_wr 1.550s 122.894us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.492m 7.685ms 1 1 100.00
V2 error hmac_error 32.970s 1.883ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 36.380s 2.808ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.520s 197.228us 1 1 100.00
hmac_long_msg 59.960s 3.439ms 1 1 100.00
hmac_back_pressure 18.660s 1.705ms 1 1 100.00
hmac_datapath_stress 5.492m 7.685ms 1 1 100.00
hmac_burst_wr 1.550s 122.894us 1 1 100.00
hmac_stress_all 8.489m 79.320ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.520s 197.228us 1 1 100.00
hmac_long_msg 59.960s 3.439ms 1 1 100.00
hmac_back_pressure 18.660s 1.705ms 1 1 100.00
hmac_datapath_stress 5.492m 7.685ms 1 1 100.00
hmac_wipe_secret 36.380s 2.808ms 1 1 100.00
hmac_test_sha256_vectors 2.714m 5.128ms 1 1 100.00
hmac_test_sha384_vectors 5.924m 22.888ms 1 1 100.00
hmac_test_sha512_vectors 18.850s 504.911us 1 1 100.00
hmac_test_hmac256_vectors 5.380s 197.036us 1 1 100.00
hmac_test_hmac384_vectors 6.640s 1.839ms 1 1 100.00
hmac_test_hmac512_vectors 9.000s 317.368us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.520s 197.228us 1 1 100.00
hmac_long_msg 59.960s 3.439ms 1 1 100.00
hmac_back_pressure 18.660s 1.705ms 1 1 100.00
hmac_datapath_stress 5.492m 7.685ms 1 1 100.00
hmac_burst_wr 1.550s 122.894us 1 1 100.00
hmac_error 32.970s 1.883ms 1 1 100.00
hmac_wipe_secret 36.380s 2.808ms 1 1 100.00
hmac_test_sha256_vectors 2.714m 5.128ms 1 1 100.00
hmac_test_sha384_vectors 5.924m 22.888ms 1 1 100.00
hmac_test_sha512_vectors 18.850s 504.911us 1 1 100.00
hmac_test_hmac256_vectors 5.380s 197.036us 1 1 100.00
hmac_test_hmac384_vectors 6.640s 1.839ms 1 1 100.00
hmac_test_hmac512_vectors 9.000s 317.368us 1 1 100.00
hmac_stress_all 8.489m 79.320ms 1 1 100.00
V2 stress_all hmac_stress_all 8.489m 79.320ms 1 1 100.00
V2 alert_test hmac_alert_test 0.550s 11.636us 1 1 100.00
V2 intr_test hmac_intr_test 0.580s 24.490us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.650s 154.686us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.650s 154.686us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.810s 64.530us 1 1 100.00
hmac_csr_rw 0.670s 42.703us 1 1 100.00
hmac_csr_aliasing 2.340s 315.490us 1 1 100.00
hmac_same_csr_outstanding 1.720s 125.156us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.810s 64.530us 1 1 100.00
hmac_csr_rw 0.670s 42.703us 1 1 100.00
hmac_csr_aliasing 2.340s 315.490us 1 1 100.00
hmac_same_csr_outstanding 1.720s 125.156us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.790s 67.791us 1 1 100.00
hmac_tl_intg_err 2.670s 257.153us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.670s 257.153us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.520s 197.228us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.500s 233.897us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 56.320s 13.408ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.870s 74.967us 1 1 100.00
TOTAL 28 28 100.00