ff105ef| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 53.390s | 1.863ms | 1 | 1 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 19.850s | 2.156ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.650s | 56.035us | 1 | 1 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.650s | 21.652us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.120s | 114.709us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 0.980s | 224.325us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 0.830s | 38.951us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.650s | 21.652us | 1 | 1 | 100.00 |
| i2c_csr_aliasing | 0.980s | 224.325us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 7 | 7 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 0.830s | 65.280us | 0 | 1 | 0.00 |
| V2 | host_stress_all | i2c_host_stress_all | 19.392s | 0 | 1 | 0.00 | |
| V2 | host_maxperf | i2c_host_perf | 2.681m | 24.622ms | 1 | 1 | 100.00 |
| V2 | host_override | i2c_host_override | 0.590s | 18.660us | 1 | 1 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 33.364s | 0 | 1 | 0.00 | |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 27.570s | 2.359ms | 1 | 1 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 0.980s | 2.165ms | 1 | 1 | 100.00 |
| i2c_host_fifo_fmt_empty | 10.690s | 534.153us | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 2.840s | 544.299us | 1 | 1 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 54.060s | 7.048ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 7.220s | 724.331us | 1 | 1 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 24.375s | 0 | 1 | 0.00 | |
| V2 | target_glitch | i2c_target_glitch | 1.950s | 557.075us | 0 | 1 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 3.319m | 25.133ms | 1 | 1 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 2.370s | 2.267ms | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 16.750s | 5.385ms | 1 | 1 | 100.00 |
| i2c_target_intr_smoke | 2.240s | 600.103us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 0.790s | 416.151us | 1 | 1 | 100.00 |
| i2c_target_fifo_reset_tx | 1.010s | 1.548ms | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 13.560s | 27.690ms | 1 | 1 | 100.00 |
| i2c_target_stress_rd | 16.750s | 5.385ms | 1 | 1 | 100.00 | ||
| i2c_target_intr_stress_wr | 2.270s | 3.400ms | 1 | 1 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 4.010s | 5.291ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 9.320s | 983.779us | 1 | 1 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.250s | 3.357ms | 1 | 1 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 18.022s | 0 | 1 | 0.00 | |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 2.250s | 580.862us | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.250s | 180.691us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 2.681m | 24.622ms | 1 | 1 | 100.00 |
| i2c_host_perf_precise | 29.490s | 1.071ms | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 7.220s | 724.331us | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 2.560s | 322.635us | 1 | 1 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 1.930s | 575.382us | 1 | 1 | 100.00 |
| i2c_target_nack_acqfull_addr | 1.620s | 2.207ms | 1 | 1 | 100.00 | ||
| i2c_target_nack_txstretch | 1.010s | 146.997us | 0 | 1 | 0.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 3.620s | 361.094us | 1 | 1 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 1.370s | 389.835us | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.590s | 48.446us | 1 | 1 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.610s | 23.683us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.140s | 54.834us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.140s | 54.834us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.650s | 56.035us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.650s | 21.652us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 0.980s | 224.325us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.870s | 43.346us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.650s | 56.035us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.650s | 21.652us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 0.980s | 224.325us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.870s | 43.346us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 31 | 38 | 81.58 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.130s | 126.764us | 1 | 1 | 100.00 |
| i2c_sec_cm | 18.016s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.130s | 126.764us | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 23.890s | 2.920ms | 0 | 1 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 0.940s | 126.072us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 9.570s | 938.512us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 39 | 50 | 78.00 |
Job returned non-zero exit code has 5 failures:
Test i2c_host_fifo_watermark has 1 failures.
0.i2c_host_fifo_watermark.82280768795950041751894769683218621492559369594939301284451520539909777510616
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 23 18:51 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_host_stress_all has 1 failures.
0.i2c_host_stress_all.93292753223337840191074613881975010679038880990859385449534470767691004815468
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 23 18:52 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_hrst has 1 failures.
0.i2c_target_hrst.109307170162549759157294552557744838431535864968561945470658714825864304589937
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 23 18:52 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_host_mode_toggle has 1 failures.
0.i2c_host_mode_toggle.26383149382219354758739567011613470081623594855253858130082160814092247282446
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 23 18:52 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_sec_cm has 1 failures.
0.i2c_sec_cm.14217562343930463771806733431464855954854764313224026750585564850473285911572
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_sec_cm/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 23 18:52 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
0.i2c_host_stress_all_with_rand_reset.58323335936600584123569326030097314311745392129948358787788480837293307672826
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2920132471 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2920132471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
0.i2c_target_stress_all_with_rand_reset.31321945002745729669265677771869216704563322468460459834042328310067324000796
Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 938512126 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 938512126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:
0.i2c_host_error_intr.47991669715033745594225306728697421142513347441794139633535738858972648100483
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 65280127 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 65280127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
0.i2c_target_glitch.64407410110908964459650633332038521026216663989541458573916985036873148000076
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 557075029 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 557075029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
0.i2c_target_unexp_stop.40551979611079745313071010692611767215556271027756033290423110507467725332651
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 126072091 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 126072091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
0.i2c_target_nack_txstretch.83725272729696211930658955967768029801527442235605343400592598255869903359989
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 146997444 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 146997444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---