KEYMGR Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.890s	143.424us	1	1	100.00
V1	random	keymgr_random	22.300s	1.656ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.900s	20.069us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.960s	14.504us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.340s	17.118ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.820s	673.778us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.590s	55.775us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.960s	14.504us	1	1	100.00
		keymgr_csr_aliasing	4.820s	673.778us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	34.450s	13.604ms	1	1	100.00
V2	sideload	keymgr_sideload	2.670s	482.245us	1	1	100.00
		keymgr_sideload_kmac	1.480s	47.370us	1	1	100.00
		keymgr_sideload_aes	46.040s	7.264ms	1	1	100.00
		keymgr_sideload_otbn	1.930s	47.663us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.890s	232.512us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.040s	104.419us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.360s	33.968us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	13.923s		0	1	0.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.910s	129.966us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.190s	177.554us	1	1	100.00
V2	stress_all	keymgr_stress_all	9.690s	1.176ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.640s	13.243us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.670s	118.355us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.540s	234.910us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.540s	234.910us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.900s	20.069us	1	1	100.00
		keymgr_csr_rw	0.960s	14.504us	1	1	100.00
		keymgr_csr_aliasing	4.820s	673.778us	1	1	100.00
		keymgr_same_csr_outstanding	1.460s	46.332us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.900s	20.069us	1	1	100.00
		keymgr_csr_rw	0.960s	14.504us	1	1	100.00
		keymgr_csr_aliasing	4.820s	673.778us	1	1	100.00
		keymgr_same_csr_outstanding	1.460s	46.332us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
		keymgr_tl_intg_err	3.000s	143.066us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	13.870s		0	1	0.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	13.870s		0	1	0.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	13.870s		0	1	0.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	13.870s		0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.350s	750.342us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.000s	143.066us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	13.870s		0	1	0.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	34.450s	13.604ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	22.300s	1.656ms	1	1	100.00
		keymgr_csr_rw	0.960s	14.504us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	22.300s	1.656ms	1	1	100.00
		keymgr_csr_rw	0.960s	14.504us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	22.300s	1.656ms	1	1	100.00
		keymgr_csr_rw	0.960s	14.504us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.040s	104.419us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.910s	129.966us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.910s	129.966us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	22.300s	1.656ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.410s	28.669us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.540s	109.119us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.040s	104.419us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.540s	109.119us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.540s	109.119us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.540s	109.119us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.160s	1.610ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.540s	109.119us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	4.080s	866.760us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test keymgr_sw_invalid_input has 1 failures.

    • 0.keymgr_sw_invalid_input.26640752384413993736260248916947165859576053566919043363833128016092604591967
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:44 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test keymgr_shadow_reg_errors has 1 failures.

    • 0.keymgr_shadow_reg_errors.15403994268161772712631011161574048404002237874490505243236057500079442064667
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:42 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.56675338242475188942733226278143457561363060947063936221571979805404059543888
      Line 772, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 866760020 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 866760020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---