ff105ef| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0.820s | 67.666us | 1 | 1 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 0.750s | 22.393us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 11.790s | 16.018ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 5.950s | 1.507ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 1.690s | 63.136us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0.750s | 22.393us | 1 | 1 | 100.00 |
| kmac_csr_aliasing | 5.950s | 1.507ms | 1 | 1 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.620s | 37.269us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.050s | 507.100us | 1 | 1 | 100.00 |
| V1 | TOTAL | 7 | 8 | 87.50 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 0 | 1 | 0.00 | ||
| V2 | burst_write | kmac_burst_write | 0 | 1 | 0.00 | ||
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 0 | 1 | 0.00 | ||
| kmac_test_vectors_sha3_256 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_sha3_384 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_sha3_512 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_shake_128 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_shake_256 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_kmac | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_kmac_xof | 0 | 1 | 0.00 | ||||
| V2 | sideload | kmac_sideload | 0 | 1 | 0.00 | ||
| V2 | app | kmac_app | 0 | 1 | 0.00 | ||
| V2 | app_with_partial_data | kmac_app_with_partial_data | 0 | 1 | 0.00 | ||
| V2 | entropy_refresh | kmac_entropy_refresh | 0 | 1 | 0.00 | ||
| V2 | error | kmac_error | 0 | 1 | 0.00 | ||
| V2 | key_error | kmac_key_error | 0 | 1 | 0.00 | ||
| V2 | sideload_invalid | kmac_sideload_invalid | 0 | 1 | 0.00 | ||
| V2 | edn_timeout_error | kmac_edn_timeout_error | 0 | 1 | 0.00 | ||
| V2 | entropy_mode_error | kmac_entropy_mode_error | 0 | 1 | 0.00 | ||
| V2 | entropy_ready_error | kmac_entropy_ready_error | 0 | 1 | 0.00 | ||
| V2 | lc_escalation | kmac_lc_escalation | 0 | 1 | 0.00 | ||
| V2 | stress_all | kmac_stress_all | 0 | 1 | 0.00 | ||
| V2 | intr_test | kmac_intr_test | 0.720s | 16.623us | 1 | 1 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0 | 1 | 0.00 | ||
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 1.640s | 338.538us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 1.640s | 338.538us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0.820s | 67.666us | 1 | 1 | 100.00 |
| kmac_csr_rw | 0.750s | 22.393us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 5.950s | 1.507ms | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 1.800s | 98.268us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0.820s | 67.666us | 1 | 1 | 100.00 |
| kmac_csr_rw | 0.750s | 22.393us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 5.950s | 1.507ms | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 1.800s | 98.268us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 3 | 26 | 11.54 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 15.802s | 0 | 1 | 0.00 | |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 15.802s | 0 | 1 | 0.00 | |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 15.802s | 0 | 1 | 0.00 | |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 15.802s | 0 | 1 | 0.00 | |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 2.060s | 133.506us | 1 | 1 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 0 | 1 | 0.00 | ||
| kmac_tl_intg_err | 2.020s | 565.719us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 2.020s | 565.719us | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 0 | 1 | 0.00 | ||
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 0 | 1 | 0.00 | ||
| V2S | sec_cm_key_sideload | kmac_sideload | 0 | 1 | 0.00 | ||
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 15.802s | 0 | 1 | 0.00 | |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 0 | 1 | 0.00 | ||
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 0 | 1 | 0.00 | ||
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 0 | 1 | 0.00 | ||
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 2 | 5 | 40.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 12 | 40 | 30.00 |
Job killed most likely because its dependent job failed. has 27 failures:
Test kmac_smoke has 1 failures.
Test kmac_long_msg_and_output has 1 failures.
Test kmac_sideload has 1 failures.
Test kmac_sideload_invalid has 1 failures.
Test kmac_burst_write has 1 failures.
... and 22 more tests.
Job timed out after * minutes has 1 failures:
default
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/build.log
Job timed out after 60 minutes
Job returned non-zero exit code has 1 failures:
0.kmac_shadow_reg_errors.29328778074432873609256688479426524696435192990351075035808031976753363263762
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255