ROM_CTRL/64KB Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.420s	1.082ms	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.380s	740.401us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.850s	214.543us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.690s	536.218us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.280s	770.620us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.719s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.850s	214.543us	1	1	100.00
		rom_ctrl_csr_aliasing	6.280s	770.620us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.310s	377.037us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.260s	700.087us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.720s	226.443us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	38.010s	4.109ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	14.040s	552.337us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	6.400s	1.027ms	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	7.210s	267.363us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	7.210s	267.363us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.380s	740.401us	1	1	100.00
		rom_ctrl_csr_rw	5.850s	214.543us	1	1	100.00
		rom_ctrl_csr_aliasing	6.280s	770.620us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.270s	1.218ms	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.380s	740.401us	1	1	100.00
		rom_ctrl_csr_rw	5.850s	214.543us	1	1	100.00
		rom_ctrl_csr_aliasing	6.280s	770.620us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.270s	1.218ms	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.388m	37.166ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	25.620s	2.251ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	7.163m	2.586ms	0	1	0.00
		rom_ctrl_tl_intg_err	15.614s		0	1	0.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	7.163m	2.586ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	7.163m	2.586ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.388m	37.166ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.388m	37.166ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.388m	37.166ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.388m	37.166ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.388m	37.166ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	7.163m	2.586ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	7.163m	2.586ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.420s	1.082ms	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.420s	1.082ms	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.420s	1.082ms	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	15.614s		0	1	0.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.388m	37.166ms	1	1	100.00
		rom_ctrl_kmac_err_chk	14.040s	552.337us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.388m	37.166ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.388m	37.166ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.388m	37.166ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	25.620s	2.251ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	7.163m	2.586ms	0	1	0.00
V2S		TOTAL			2	4	50.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	3.724m	18.994ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	19	84.21

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test rom_ctrl_tl_intg_err has 1 failures.

    • 0.rom_ctrl_tl_intg_err.17345120649717653871611100572347630541336398115838683820337028249797986228259
      Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:53 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test rom_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.rom_ctrl_csr_mem_rw_with_rand_reset.24744533024244705407742195576496023309101851198443711511454802378474084993954
      Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:53 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.87887005631478737455145918464059750013179460998341416998608874554725092698975
      Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 3382695ps failed at 3382695ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 3382695ps failed at 3382695ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'