RV_TIMER Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.820s	2.372ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.560s	230.833us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.570s	13.291us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.240s	92.589us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.650s	67.434us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.940s	44.325us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.570s	13.291us	1	1	100.00
		rv_timer_csr_aliasing	0.650s	67.434us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.570s	143.830us	1	1	100.00
V2	disabled	rv_timer_disabled	20.466s		0	1	0.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.370s	2.709ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.370s	2.709ms	1	1	100.00
V2	stress	rv_timer_stress_all	7.340s	5.953ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.540s	43.219us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.530s	75.361us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.000s	59.419us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.000s	59.419us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.560s	230.833us	1	1	100.00
		rv_timer_csr_rw	0.570s	13.291us	1	1	100.00
		rv_timer_csr_aliasing	0.650s	67.434us	1	1	100.00
		rv_timer_same_csr_outstanding	0.720s	147.088us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.560s	230.833us	1	1	100.00
		rv_timer_csr_rw	0.570s	13.291us	1	1	100.00
		rv_timer_csr_aliasing	0.650s	67.434us	1	1	100.00
		rv_timer_same_csr_outstanding	0.720s	147.088us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.780s	166.862us	1	1	100.00
		rv_timer_tl_intg_err	0.730s	98.152us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.730s	98.152us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.510s	14.980us	1	1	100.00
V3	max_value	rv_timer_max	0.610s	184.926us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	31.910s	5.353ms	1	1	100.00
V3		TOTAL			2	3	66.67
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.23814214672986357617158877779983670621094009851179092812892482261189837810571
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 184925563 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 184925563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 1 failures:

  • Test rv_timer_disabled has 1 failures.

    • 0.rv_timer_disabled.14774156467636449055620321899508340726589450483515284014532705287252480973172
      Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log

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        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255