SPI_DEVICE/1R1W Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	33.030s	2.699ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.770s	60.789us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.300s	90.547us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	21.230s	2.364ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	9.410s	215.277us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.300s	53.010us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.300s	90.547us	1	1	100.00
		spi_device_csr_aliasing	9.410s	215.277us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.600s	31.067us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	0.970s	115.044us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.760s	39.502us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.640s	5.382us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.650s	3.177us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.340s	715.195us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.340s	715.195us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.040s	15.885ms	1	1	100.00
		spi_device_tpm_sts_read	0.740s	54.115us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.760s	13.685ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.620s	32.207us	1	1	100.00
		spi_device_flash_all	16.412s		0	1	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.780s	191.343us	1	1	100.00
		spi_device_flash_all	16.412s		0	1	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.780s	191.343us	1	1	100.00
		spi_device_flash_all	16.412s		0	1	0.00
V2	cmd_info_slots	spi_device_flash_all	16.412s		0	1	0.00
V2	cmd_read_status	spi_device_intercept	1.590s	149.090us	1	1	100.00
		spi_device_flash_all	16.412s		0	1	0.00
V2	cmd_read_jedec	spi_device_intercept	1.590s	149.090us	1	1	100.00
		spi_device_flash_all	16.412s		0	1	0.00
V2	cmd_read_sfdp	spi_device_intercept	1.590s	149.090us	1	1	100.00
		spi_device_flash_all	16.412s		0	1	0.00
V2	cmd_fast_read	spi_device_intercept	1.590s	149.090us	1	1	100.00
		spi_device_flash_all	16.412s		0	1	0.00
V2	cmd_read_pipeline	spi_device_intercept	1.590s	149.090us	1	1	100.00
		spi_device_flash_all	16.412s		0	1	0.00
V2	flash_cmd_upload	spi_device_upload	9.560s	13.657ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	9.410s	1.610ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	9.410s	1.610ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	9.410s	1.610ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.660s	427.292us	1	1	100.00
		spi_device_read_buffer_direct	2.750s	561.137us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	9.410s	1.610ms	1	1	100.00
		spi_device_flash_all	16.412s		0	1	0.00
V2	quad_spi	spi_device_flash_all	16.412s		0	1	0.00
V2	dual_spi	spi_device_flash_all	16.412s		0	1	0.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.233s		0	1	0.00
V2	write_enable_disable	spi_device_cfg_cmd	16.233s		0	1	0.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	33.030s	2.699ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.850s	6.476ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.624m	237.192ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.650s	13.883us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.650s	11.557us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.480s	2.925ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.480s	2.925ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.770s	60.789us	1	1	100.00
		spi_device_csr_rw	1.300s	90.547us	1	1	100.00
		spi_device_csr_aliasing	9.410s	215.277us	1	1	100.00
		spi_device_same_csr_outstanding	1.900s	45.617us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.770s	60.789us	1	1	100.00
		spi_device_csr_rw	1.300s	90.547us	1	1	100.00
		spi_device_csr_aliasing	9.410s	215.277us	1	1	100.00
		spi_device_same_csr_outstanding	1.900s	45.617us	1	1	100.00
V2		TOTAL			18	22	81.82
V2S	tl_intg_err	spi_device_sec_cm	0.890s	281.843us	1	1	100.00
		spi_device_tl_intg_err	12.610s	1.228ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.610s	1.228ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.156m	36.186ms	1	1	100.00
		TOTAL			29	33	87.88

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test spi_device_cfg_cmd has 1 failures.

    • 0.spi_device_cfg_cmd.73933716780713629561124808687397348805623003764146536590250468630546575441400
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:50 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test spi_device_flash_all has 1 failures.

    • 0.spi_device_flash_all.42622824375011475181233486738452540905407727976003712430146578288820051881591
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:50 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.58338456249537458627838604356719801056261978863634292467769764113564368799686
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4563576 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[34])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4563576 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4563576 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[930])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.20296097294924296169230795210695472993691506899160470427180874293598792168832
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    963377 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3329c9 [1100110010100111001001] vs 0x0 [0])
        UVM_ERROR @   1001377 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x50c94c [10100001100100101001100] vs 0x0 [0])
        UVM_ERROR @   1096377 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x56b91e [10101101011100100011110] vs 0x0 [0])
        UVM_ERROR @   1156377 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd6ab97 [110101101010101110010111] vs 0x0 [0])
        UVM_ERROR @   1197377 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x381942 [1110000001100101000010] vs 0x0 [0])