SPI_DEVICE/2P Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	25.130s	7.439ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.900s	34.084us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.040s	92.387us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	13.400s	1.458ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.040s	118.382us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.150s	274.728us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.040s	92.387us	1	1	100.00
		spi_device_csr_aliasing	5.040s	118.382us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	23.413us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.260s	94.843us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.740s	240.885us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.860s	24.649us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.640s	31.524us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.610s	356.947us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.610s	356.947us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.150s	224.552us	1	1	100.00
		spi_device_tpm_sts_read	0.720s	44.988us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	7.830s	876.994us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.590s	8.703ms	1	1	100.00
		spi_device_flash_all	36.949s		0	1	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.790s	324.176us	1	1	100.00
		spi_device_flash_all	36.949s		0	1	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.790s	324.176us	1	1	100.00
		spi_device_flash_all	36.949s		0	1	0.00
V2	cmd_info_slots	spi_device_flash_all	36.949s		0	1	0.00
V2	cmd_read_status	spi_device_intercept	4.100s	1.369ms	1	1	100.00
		spi_device_flash_all	36.949s		0	1	0.00
V2	cmd_read_jedec	spi_device_intercept	4.100s	1.369ms	1	1	100.00
		spi_device_flash_all	36.949s		0	1	0.00
V2	cmd_read_sfdp	spi_device_intercept	4.100s	1.369ms	1	1	100.00
		spi_device_flash_all	36.949s		0	1	0.00
V2	cmd_fast_read	spi_device_intercept	4.100s	1.369ms	1	1	100.00
		spi_device_flash_all	36.949s		0	1	0.00
V2	cmd_read_pipeline	spi_device_intercept	4.100s	1.369ms	1	1	100.00
		spi_device_flash_all	36.949s		0	1	0.00
V2	flash_cmd_upload	spi_device_upload	4.440s	755.248us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	10.230s	4.210ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	10.230s	4.210ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	10.230s	4.210ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	13.490s	2.968ms	1	1	100.00
		spi_device_read_buffer_direct	8.300s	1.679ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	10.230s	4.210ms	1	1	100.00
		spi_device_flash_all	36.949s		0	1	0.00
V2	quad_spi	spi_device_flash_all	36.949s		0	1	0.00
V2	dual_spi	spi_device_flash_all	36.949s		0	1	0.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.480s	4.987ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.480s	4.987ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	25.130s	7.439ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.400m	29.179ms	1	1	100.00
V2	stress_all	spi_device_stress_all	44.820s	8.260ms	1	1	100.00
V2	alert_test	spi_device_alert_test	19.981s		0	1	0.00
V2	intr_test	spi_device_intr_test	0.670s	127.255us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.550s	82.544us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.550s	82.544us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.900s	34.084us	1	1	100.00
		spi_device_csr_rw	1.040s	92.387us	1	1	100.00
		spi_device_csr_aliasing	5.040s	118.382us	1	1	100.00
		spi_device_same_csr_outstanding	1.310s	58.494us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.900s	34.084us	1	1	100.00
		spi_device_csr_rw	1.040s	92.387us	1	1	100.00
		spi_device_csr_aliasing	5.040s	118.382us	1	1	100.00
		spi_device_same_csr_outstanding	1.310s	58.494us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	0.940s	1.816ms	1	1	100.00
		spi_device_tl_intg_err	8.450s	202.544us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	8.450s	202.544us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	32.810s	8.432ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test spi_device_flash_all has 1 failures.

    • 0.spi_device_flash_all.19670927364412363869938087276368834379751931232060887862289944326674939549462
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:44 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test spi_device_alert_test has 1 failures.

    • 0.spi_device_alert_test.115504488699778714673056080804040402997661716847015175332947232743522084136551
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:44 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255