SPI_HOST Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 26.000s 0 1 0.00
V1 csr_hw_reset spi_host_csr_hw_reset 22.000s 0 1 0.00
V1 csr_rw spi_host_csr_rw 26.000s 0 1 0.00
V1 csr_bit_bash spi_host_csr_bit_bash 29.000s 0 1 0.00
V1 csr_aliasing spi_host_csr_aliasing 37.000s 0 1 0.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 29.000s 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 26.000s 0 1 0.00
spi_host_csr_aliasing 37.000s 0 1 0.00
V1 mem_walk spi_host_mem_walk 13.000s 0 1 0.00
V1 mem_partial_access spi_host_mem_partial_access 21.000s 0 1 0.00
V1 TOTAL 0 8 0.00
V2 performance spi_host_performance 29.000s 0 1 0.00
V2 error_event_intr spi_host_overflow_underflow 20.000s 0 1 0.00
spi_host_error_cmd 29.000s 0 1 0.00
spi_host_event 21.000s 0 1 0.00
V2 clock_rate spi_host_speed 11.000s 192.720us 1 1 100.00
V2 speed spi_host_speed 11.000s 192.720us 1 1 100.00
V2 chip_select_timing spi_host_speed 11.000s 192.720us 1 1 100.00
V2 sw_reset spi_host_sw_reset 33.000s 0 1 0.00
V2 passthrough_mode spi_host_passthrough_mode 30.000s 0 1 0.00
V2 cpol_cpha spi_host_speed 11.000s 192.720us 1 1 100.00
V2 full_cycle spi_host_speed 11.000s 192.720us 1 1 100.00
V2 duplex spi_host_smoke 26.000s 0 1 0.00
V2 tx_rx_only spi_host_smoke 26.000s 0 1 0.00
V2 stress_all spi_host_stress_all 14.000s 0 1 0.00
V2 spien spi_host_spien 29.000s 0 1 0.00
V2 stall spi_host_status_stall 25.000s 0 1 0.00
V2 Idlecsbactive spi_host_idlecsbactive 29.000s 0 1 0.00
V2 data_fifo_status spi_host_overflow_underflow 20.000s 0 1 0.00
V2 alert_test spi_host_alert_test 29.000s 0 1 0.00
V2 intr_test spi_host_intr_test 45.000s 0 1 0.00
V2 tl_d_oob_addr_access spi_host_tl_errors 46.000s 0 1 0.00
V2 tl_d_illegal_access spi_host_tl_errors 46.000s 0 1 0.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 22.000s 0 1 0.00
spi_host_csr_rw 26.000s 0 1 0.00
spi_host_csr_aliasing 37.000s 0 1 0.00
spi_host_same_csr_outstanding 29.000s 0 1 0.00
V2 tl_d_partial_access spi_host_csr_hw_reset 22.000s 0 1 0.00
spi_host_csr_rw 26.000s 0 1 0.00
spi_host_csr_aliasing 37.000s 0 1 0.00
spi_host_same_csr_outstanding 29.000s 0 1 0.00
V2 TOTAL 1 15 6.67
V2S tl_intg_err spi_host_tl_intg_err 33.000s 0 1 0.00
spi_host_sec_cm 33.000s 0 1 0.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 33.000s 0 1 0.00
V2S TOTAL 0 2 0.00
Unmapped tests spi_host_upper_range_clkdiv 42.000s 0 1 0.00
TOTAL 1 26 3.85

Failure Buckets