SRAM_CTRL/MAIN Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	18.290s	2.229ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.640s	17.318us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.650s	14.361us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	0.970s	87.691us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.670s	18.463us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.650s	354.075us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.650s	14.361us	1	1	100.00
		sram_ctrl_csr_aliasing	0.670s	18.463us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.409m	4.942ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	48.600s	1.424ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.211m	530.822ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.724m	19.695ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	16.040m	166.633ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.573m	4.812ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	15.390s	4.427ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.883m	5.944ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	42.820s	2.562ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.360m	43.461ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	34.910s	5.034ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	19.740s	12.351ms	1	1	100.00
		sram_ctrl_throughput_w_readback	4.500s	703.795us	1	1	100.00
V2	regwen	sram_ctrl_regwen	59.080s	8.697ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.620s	6.728ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	34.734m	436.925ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.660s	59.252us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.750s	419.373us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.750s	419.373us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.640s	17.318us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	14.361us	1	1	100.00
		sram_ctrl_csr_aliasing	0.670s	18.463us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.690s	20.325us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.640s	17.318us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	14.361us	1	1	100.00
		sram_ctrl_csr_aliasing	0.670s	18.463us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.690s	20.325us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	28.990s	7.528ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	17.586s		0	1	0.00
		sram_ctrl_tl_intg_err	1.230s	191.091us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	17.586s		0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.230s	191.091us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	59.080s	8.697ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	59.080s	8.697ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.650s	14.361us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.883m	5.944ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.883m	5.944ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.883m	5.944ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	15.390s	4.427ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.520s	696.381us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	28.990s	7.528ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.780s	1.412ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	18.290s	2.229ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	18.290s	2.229ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.883m	5.944ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	17.586s		0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	15.390s	4.427ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	17.586s		0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	17.586s		0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	18.290s	2.229ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	17.586s		0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	55.820s	11.501ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.40348128466801336737434186850993229863574525710383756841156080450699661126510
      Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

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        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255