SRAM_CTRL/RET Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.870s	456.692us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.620s	21.697us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.640s	14.948us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.030s	125.201us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.690s	34.264us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.890s	39.468us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.640s	14.948us	1	1	100.00
		sram_ctrl_csr_aliasing	0.690s	34.264us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.310s	672.528us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.900s	816.006us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.902m	16.813ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	15.879s		0	1	0.00
V2	bijection	sram_ctrl_bijection	21.320s	12.247ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.568s		0	1	0.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.740s	1.150ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.534m	42.545ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	15.350s	1.451ms	1	1	100.00
		sram_ctrl_partial_access_b2b	11.977s		0	1	0.00
V2	max_throughput	sram_ctrl_max_throughput	21.700s	220.407us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	34.780s	300.194us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.670s	105.153us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.240m	3.151ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.690s	137.833us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	25.297m	94.212ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.600s	14.405us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.260s	98.853us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.260s	98.853us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.620s	21.697us	1	1	100.00
		sram_ctrl_csr_rw	0.640s	14.948us	1	1	100.00
		sram_ctrl_csr_aliasing	0.690s	34.264us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.660s	21.992us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.620s	21.697us	1	1	100.00
		sram_ctrl_csr_rw	0.640s	14.948us	1	1	100.00
		sram_ctrl_csr_aliasing	0.690s	34.264us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.660s	21.992us	1	1	100.00
V2		TOTAL			14	17	82.35
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.180s	422.261us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.560s	7.147us	0	1	0.00
		sram_ctrl_tl_intg_err	1.150s	102.210us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.560s	7.147us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.150s	102.210us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.240m	3.151ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.240m	3.151ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.640s	14.948us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.534m	42.545ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.534m	42.545ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.534m	42.545ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.740s	1.150ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.810s	90.535us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.180s	422.261us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.800s	96.055us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.870s	456.692us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.870s	456.692us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.534m	42.545ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.560s	7.147us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.740s	1.150ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.560s	7.147us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.560s	7.147us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.870s	456.692us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.560s	7.147us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.760s	472.308us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	31	87.10

Failure Buckets

• Job returned non-zero exit code has 3 failures:

  • Test sram_ctrl_stress_pipeline has 1 failures.

    • 0.sram_ctrl_stress_pipeline.22391413244817196048095157716632742855082328672786652986518465132818254888874
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:44 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_partial_access_b2b has 1 failures.

    • 0.sram_ctrl_partial_access_b2b.18540763967135067319199066503838123554925892060103357559129558454856851584640
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:44 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_access_during_key_req has 1 failures.

    • 0.sram_ctrl_access_during_key_req.72047564200558166173755950771651866787697322619085255806341789957139232923951
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 18:44 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.47646101673687065981921767563671685157879986684885986261404913202764558571092
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   7146942 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   7146942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---