ff105ef| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 1.580s | 2.121ms | 1 | 1 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 1.850s | 2.454ms | 1 | 1 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 0.770s | 2.555ms | 1 | 1 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 5.100s | 2.546ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | sysrst_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| sysrst_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | TOTAL | 4 | 9 | 44.44 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 59.620s | 143.387ms | 1 | 1 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 9.140s | 26.366ms | 1 | 1 | 100.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 7.440s | 3.879ms | 1 | 1 | 100.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 1.810s | 2.965ms | 1 | 1 | 100.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 1.760s | 2.525ms | 1 | 1 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 2.430s | 2.145ms | 1 | 1 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 1.560s | 2.443ms | 1 | 1 | 100.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 4.740s | 2.612ms | 1 | 1 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 1.231m | 1.611s | 1 | 1 | 100.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 28.516s | 0 | 1 | 0.00 | |
| V2 | stress_all | sysrst_ctrl_stress_all | 6.900s | 7.151ms | 1 | 1 | 100.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 3.970s | 2.013ms | 1 | 1 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 0 | 1 | 0.00 | ||
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| sysrst_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| sysrst_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| sysrst_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| sysrst_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| sysrst_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| sysrst_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 11 | 15 | 73.33 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 33.300s | 42.051ms | 1 | 1 | 100.00 |
| sysrst_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 2.970s | 5.034ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 17 | 27 | 62.96 |
Job killed most likely because its dependent job failed. has 9 failures:
Test sysrst_ctrl_tl_errors has 1 failures.
Test sysrst_ctrl_tl_intg_err has 1 failures.
Test sysrst_ctrl_intr_test has 1 failures.
Test sysrst_ctrl_csr_hw_reset has 1 failures.
Test sysrst_ctrl_csr_rw has 1 failures.
... and 4 more tests.
Job timed out after * minutes has 1 failures:
cover_reg_top
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cover_reg_top/build.log
Job timed out after 60 minutes
Job returned non-zero exit code has 1 failures:
0.sysrst_ctrl_feature_disable.48506386618820747105982250743254293263023886128033371383565660617604988080398
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest/run.log
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255