UART Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.290s	880.386us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.570s	17.473us	1	1	100.00
V1	csr_rw	uart_csr_rw	20.260s		0	1	0.00
V1	csr_bit_bash	uart_csr_bit_bash	1.660s	143.478us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.600s	69.552us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.710s	98.116us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	20.260s		0	1	0.00
		uart_csr_aliasing	0.600s	69.552us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	base_random_seq	uart_tx_rx	3.166m	102.527ms	1	1	100.00
V2	parity	uart_smoke	2.290s	880.386us	1	1	100.00
		uart_tx_rx	3.166m	102.527ms	1	1	100.00
V2	parity_error	uart_intr	20.010s	19.949ms	1	1	100.00
		uart_rx_parity_err	2.973m	160.269ms	1	1	100.00
V2	watermark	uart_tx_rx	3.166m	102.527ms	1	1	100.00
		uart_intr	20.010s	19.949ms	1	1	100.00
V2	fifo_full	uart_fifo_full	21.220s	68.369ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	17.820s	40.026ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	15.580s	161.234ms	1	1	100.00
V2	rx_frame_err	uart_intr	20.010s	19.949ms	1	1	100.00
V2	rx_break_err	uart_intr	20.010s	19.949ms	1	1	100.00
V2	rx_timeout	uart_intr	20.010s	19.949ms	1	1	100.00
V2	perf	uart_perf	47.670s	9.361ms	1	1	100.00
V2	sys_loopback	uart_loopback	11.700s	8.813ms	1	1	100.00
V2	line_loopback	uart_loopback	11.700s	8.813ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	0.600s	43.927us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	0.720s	708.225us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.010s	1.012ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	17.100s	3.710ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.736m	240.898ms	1	1	100.00
V2	stress_all	uart_stress_all	37.170s	62.057ms	1	1	100.00
V2	alert_test	uart_alert_test	0.550s	39.847us	1	1	100.00
V2	intr_test	uart_intr_test	0.580s	26.323us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.740s	131.500us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.740s	131.500us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.570s	17.473us	1	1	100.00
		uart_csr_rw	20.260s		0	1	0.00
		uart_csr_aliasing	0.600s	69.552us	1	1	100.00
		uart_same_csr_outstanding	0.630s	18.370us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.570s	17.473us	1	1	100.00
		uart_csr_rw	20.260s		0	1	0.00
		uart_csr_aliasing	0.600s	69.552us	1	1	100.00
		uart_same_csr_outstanding	0.630s	18.370us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.750s	125.604us	1	1	100.00
		uart_tl_intg_err	0.850s	73.157us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.850s	73.157us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	41.570s	29.359ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.78757729969540033187079968027451137882378974549102367471938416648135549008113
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @  10023427 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  18544465 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  26905933 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  27288901 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  27650593 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

• Job returned non-zero exit code has 1 failures:

  • Test uart_csr_rw has 1 failures.

    • 0.uart_csr_rw.31520618442160648813053452860086597248268384424364360625699127702003533586122
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_csr_rw/latest/run.log

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        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255