CHIP Simulation Results

Tuesday September 23 2025 18:39:33 UTC

GitHub Revision: ff105ef

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	9.857s		0	1	0.00
		chip_sw_example_rom	14.431s		0	1	0.00
		chip_sw_example_manufacturer	10.115s		0	1	0.00
		chip_sw_example_concurrency	9.814s		0	1	0.00
V1	csr_hw_reset	chip_csr_hw_reset	2.003m	4.603ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.321m	5.985ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.234m	6.423ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	36.916m	28.683ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	53.470s	2.437ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	36.916m	28.683ms	1	1	100.00
		chip_csr_rw	5.321m	5.985ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	3.810s	49.794us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	13.661s		0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	13.661s		0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	13.661s		0	1	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	9.815s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	9.815s		0	1	0.00
		chip_sw_uart_tx_rx_idx1	9.831s		0	1	0.00
		chip_sw_uart_tx_rx_idx2	9.929s		0	1	0.00
		chip_sw_uart_tx_rx_idx3	10.182s		0	1	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.269s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	13.239s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.527s		0	1	0.00
V1		TOTAL			5	18	27.78
V2	chip_pin_mux	chip_padctrl_attributes	2.609m	5.384ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.609m	5.384ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	11.511s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	11.058s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	9.559s		0	1	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	14.441s		0	1	0.00
		chip_tap_straps_testunlock0	14.158s		0	1	0.00
		chip_tap_straps_rma	14.444s		0	1	0.00
		chip_tap_straps_prod	14.443s		0	1	0.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	9.713s		0	1	0.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	9.663s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	12.750s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	12.750s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	14.366s		0	1	0.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	21.051s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.569s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	12.916s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.298s		0	1	0.00
		chip_sw_aes_enc_jitter_en	13.765s		0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	13.658s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	14.091s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	14.711s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	14.263s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.110s		0	1	0.00
		chip_sw_clkmgr_jitter	14.212s		0	1	0.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	14.298s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	13.575s		0	1	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	13.656s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	13.639s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	13.656s		0	1	0.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	19.813s		0	1	0.00
		chip_sw_aes_smoketest	18.747s		0	1	0.00
		chip_sw_aon_timer_smoketest	13.975s		0	1	0.00
		chip_sw_clkmgr_smoketest	18.862s		0	1	0.00
		chip_sw_csrng_smoketest	19.281s		0	1	0.00
		chip_sw_entropy_src_smoketest	18.535s		0	1	0.00
		chip_sw_gpio_smoketest	23.336s		0	1	0.00
		chip_sw_hmac_smoketest	18.587s		0	1	0.00
		chip_sw_kmac_smoketest	13.215s		0	1	0.00
		chip_sw_otbn_smoketest	17.607s		0	1	0.00
		chip_sw_pwrmgr_smoketest	17.730s		0	1	0.00
		chip_sw_pwrmgr_usbdev_smoketest	17.343s		0	1	0.00
		chip_sw_rv_plic_smoketest	18.201s		0	1	0.00
		chip_sw_rv_timer_smoketest	12.687s		0	1	0.00
		chip_sw_rstmgr_smoketest	22.619s		0	1	0.00
		chip_sw_sram_ctrl_smoketest	17.615s		0	1	0.00
		chip_sw_uart_smoketest	16.857s		0	1	0.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	18.420s		0	1	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	24.444s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	16.416s		0	1	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	20.180s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	24.457s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	21.543s		0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	22.083s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	14.680s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	14.659s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	46.790s	2.441ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	46.790s	2.441ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	36.916m	28.683ms	1	1	100.00
		chip_same_csr_outstanding	30.274m	30.963ms	1	1	100.00
		chip_csr_hw_reset	2.003m	4.603ms	1	1	100.00
		chip_csr_rw	5.321m	5.985ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	36.916m	28.683ms	1	1	100.00
		chip_same_csr_outstanding	30.274m	30.963ms	1	1	100.00
		chip_csr_hw_reset	2.003m	4.603ms	1	1	100.00
		chip_csr_rw	5.321m	5.985ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	29.760s	1.671ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.130s	40.801us	1	1	100.00
		xbar_smoke_large_delays	36.750s	6.707ms	1	1	100.00
		xbar_smoke_slow_rsp	30.152s		0	1	0.00
		xbar_random_zero_delays	22.080s	550.381us	1	1	100.00
		xbar_random_large_delays	3.812m	42.699ms	1	1	100.00
		xbar_random_slow_rsp	3.669m	28.895ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	14.860s	239.780us	1	1	100.00
		xbar_error_and_unmapped_addr	4.980s	126.999us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	39.970s	2.475ms	1	1	100.00
		xbar_error_and_unmapped_addr	4.980s	126.999us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	49.270s	2.858ms	1	1	100.00
		xbar_access_same_device_slow_rsp	7.908m	63.815ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	15.170s	410.312us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.447m	12.542ms	1	1	100.00
		xbar_stress_all_with_error	6.800s	109.792us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.160m	799.495us	1	1	100.00
		xbar_stress_all_with_reset_error	18.990s	101.316us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	20.180s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	20.066s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	20.555s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	22.547s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	22.214s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	22.316s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	22.629s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	22.031s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	21.919s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	21.206s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	21.038s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	21.471s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	20.123s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	21.631s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	20.166s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	21.507s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	20.802s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	19.666s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	19.725s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	10.291s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.430s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	23.122s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.083s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.379s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	24.251s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	23.170s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	23.816s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.220s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	22.850s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	23.871s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	24.358s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	23.232s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	23.389s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	22.095s		0	1	0.00
		rom_e2e_asm_init_dev	22.361s		0	1	0.00
		rom_e2e_asm_init_prod	22.364s		0	1	0.00
		rom_e2e_asm_init_prod_end	23.171s		0	1	0.00
		rom_e2e_asm_init_rma	22.305s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	20.625s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.013s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	18.317s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	21.218s		0	1	0.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	14.647s		0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	14.647s		0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	14.706s		0	1	0.00
		chip_sw_aes_enc_jitter_en	13.765s		0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	14.608s		0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	14.234s		0	1	0.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	14.518s		0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.233s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	13.704s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	9.783s		0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	13.416s		0	1	0.00
		chip_plic_all_irqs_10	13.761s		0	1	0.00
		chip_plic_all_irqs_20	13.569s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.253s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.774s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	13.891s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.170s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.899s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.249s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.608s		0	1	0.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.765s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.349s		0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	15.235s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	17.730s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	15.235s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.244s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.244s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	15.064s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	14.234s		0	1	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	14.353s		0	1	0.00
		chip_sw_aes_idle	14.234s		0	1	0.00
		chip_sw_hmac_enc_idle	14.260s		0	1	0.00
		chip_sw_kmac_idle	14.153s		0	1	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.421s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.225s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	14.504s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.501s		0	1	0.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.417s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.286s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.349s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.139s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.505s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.502s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.127s		0	1	0.00
		chip_sw_ast_clk_outputs	14.366s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.210s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.139s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.505s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.569s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	12.916s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.298s		0	1	0.00
		chip_sw_aes_enc_jitter_en	13.765s		0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	13.658s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	14.091s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	14.711s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	14.263s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.110s		0	1	0.00
		chip_sw_clkmgr_jitter	14.212s		0	1	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	14.153s		0	1	0.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	14.287s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	13.936s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.995s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	13.937s		0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	14.149s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	13.998s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	14.074s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	13.938s		0	1	0.00
		chip_sw_flash_init_reduced_freq	14.010s		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.006s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	14.366s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	14.060s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	14.212s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	9.783s		0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.249s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.144s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.901s		0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	14.841s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	13.777s		0	1	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.609s		0	1	0.00
		chip_sw_entropy_src_ast_rng_req	14.139s		0	1	0.00
		chip_sw_edn_entropy_reqs	13.779s		0	1	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	14.139s		0	1	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.144s		0	1	0.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	14.323s		0	1	0.00
V2	chip_sw_flash_init	chip_sw_flash_init	12.793s		0	1	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	13.142s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	12.916s		0	1	0.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.444s		0	1	0.00
		chip_sw_flash_ctrl_ops_jitter_en	13.569s		0	1	0.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	12.489s		0	1	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	12.793s		0	1	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	12.951s		0	1	0.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	13.247s		0	1	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	13.302s		0	1	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	12.489s		0	1	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	13.302s		0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	13.302s		0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	13.302s		0	1	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	13.302s		0	1	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	9.783s		0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.940m	7.765ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	12.448s		0	1	0.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	14.143s		0	1	0.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	14.143s		0	1	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	14.207s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	14.091s		0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	14.260s		0	1	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	13.609s		0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	13.714s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.052s		0	1	0.00
		chip_sw_i2c_host_tx_rx_idx1	10.426s		0	1	0.00
		chip_sw_i2c_host_tx_rx_idx2	10.439s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.681s		0	1	0.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	13.247s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	14.711s		0	1	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	14.174s		0	1	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	14.518s		0	1	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	14.172s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	14.604s		0	1	0.00
		chip_sw_kmac_mode_kmac	14.191s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	14.263s		0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	13.247s		0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	15.460s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	14.057s		0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	12.366s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	14.153s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	13.704s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	14.441s		0	1	0.00
		chip_tap_straps_rma	14.444s		0	1	0.00
		chip_tap_straps_prod	14.443s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	12.061s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	15.460s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	15.460s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	15.460s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.842s		0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	13.302s		0	1	0.00
		chip_sw_flash_rma_unlocked	12.489s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.971s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.679s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.090s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.586s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.460s		0	1	0.00
		chip_sw_keymgr_key_derivation	13.247s		0	1	0.00
		chip_sw_rom_ctrl_integrity_check	13.879s		0	1	0.00
		chip_sw_sram_ctrl_execution_main	14.038s		0	1	0.00
		chip_prim_tl_access	2.940m	7.765ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.210s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.286s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.349s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.139s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.505s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.502s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.127s		0	1	0.00
		chip_tap_straps_dev	14.441s		0	1	0.00
		chip_tap_straps_rma	14.444s		0	1	0.00
		chip_tap_straps_prod	14.443s		0	1	0.00
		chip_rv_dm_lc_disabled	4.642m	11.907ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	15.461s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	15.581s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	15.635s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	15.631s		0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	15.487s		0	1	0.00
		chip_rv_dm_lc_disabled	4.642m	11.907ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	15.448s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.246s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	15.694s		0	1	0.00
		chip_sw_lc_walkthrough_rma	15.303s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	15.487s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	15.619s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	15.631s		0	1	0.00
		rom_volatile_raw_unlock	18.896s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	14.646s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.298s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	14.353s		0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	14.353s		0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	14.353s		0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	14.118s		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	15.460s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	12.793s		0	1	0.00
		chip_sw_otbn_mem_scramble	14.118s		0	1	0.00
		chip_sw_keymgr_key_derivation	13.247s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	14.171s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	14.088s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	12.793s		0	1	0.00
		chip_sw_otbn_mem_scramble	14.118s		0	1	0.00
		chip_sw_keymgr_key_derivation	13.247s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	14.171s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	14.088s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	15.460s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.163s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	12.061s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.971s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.679s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.090s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.586s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.460s		0	1	0.00
		chip_prim_tl_access	2.940m	7.765ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.940m	7.765ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.525s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	14.539s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.163s		0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	14.008s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	15.117s		0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	14.817s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.167s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.060s		0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	15.244s		0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	15.236s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.656s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	14.539s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	15.183s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	14.698s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	15.175s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	14.872s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	15.178s		0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	15.540s		0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs	14.826s		0	1	0.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	13.620s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	14.820s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	9.783s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	13.879s		0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	13.879s		0	1	0.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.826s		0	1	0.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	15.178s		0	1	0.00
		chip_sw_pwrmgr_wdog_reset	14.656s		0	1	0.00
		chip_sw_pwrmgr_smoketest	17.730s		0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	10.778s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	14.719s		0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	13.017s		0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.774s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	10.886s		0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	9.783s		0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.608s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	13.821s		0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	14.593s		0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	14.156s		0	1	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	14.088s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	14.719s		0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	14.719s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	38.831s		0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	9.620m	13.997ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	10.778s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	14.177s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	14.450s		0	1	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	14.444s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.642m	11.907ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	13.416s		0	1	0.00
		chip_plic_all_irqs_10	13.761s		0	1	0.00
		chip_plic_all_irqs_20	13.569s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	12.080s		0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	15.227s		0	1	0.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	20.180s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.070s		0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	14.038s		0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	14.243s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	14.468s		0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	14.171s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.110s		0	1	0.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	14.046s		0	1	0.00
		chip_sw_sleep_sram_ret_contents_scramble	13.775s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	14.038s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	9.783s		0	1	0.00
		chip_sw_data_integrity_escalation	12.750s		0	1	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	15.540s		0	1	0.00
		chip_sw_sysrst_ctrl_reset	14.381s		0	1	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	14.218s		0	1	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	14.317s		0	1	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	14.683s		0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	14.381s		0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	14.381s		0	1	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	14.355s		0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	14.355s		0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	14.384s		0	1	0.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	14.647s		0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	14.707s		0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	14.988s		0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	14.497s		0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	14.662s		0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.526s		0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	16.094s		0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	15.249s		0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	14.710s		0	1	0.00
V2		TOTAL			20	275	7.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	13.818s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	14.439s		0	1	0.00
V2S		TOTAL			0	2	0.00
V3	chip_sw_coremark	chip_sw_coremark	13.601s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	21.640s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	23.113s		0	1	0.00
		rom_e2e_jtag_debug_dev	23.707s		0	1	0.00
		rom_e2e_jtag_debug_rma	23.113s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	23.756s		0	1	0.00
		rom_e2e_jtag_inject_dev	21.818s		0	1	0.00
		rom_e2e_jtag_inject_rma	20.737s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	24.608s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	14.212s		0	1	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	14.617s		0	1	0.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.909s		0	1	0.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.788s		0	1	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	14.617s		0	1	0.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	20.669s		0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	15.463s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	15.714s		0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	13.871s		0	1	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	15.227s		0	1	0.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.826s		0	1	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	23.113s		0	1	0.00
		rom_e2e_jtag_debug_dev	23.707s		0	1	0.00
		rom_e2e_jtag_debug_rma	23.113s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	14.111s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	9.783s		0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	15.107s		0	1	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	15.107s		0	1	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	14.026s		0	1	0.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	9.815s		0	1	0.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	15.828s		0	1	0.00
V3		TOTAL			0	23	0.00
	Unmapped tests	chip_sival_flash_info_access	10.021s		0	1	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	14.152s		0	1	0.00
		chip_sw_otp_ctrl_rot_auth_config	15.591s		0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	15.590s		0	1	0.00
		chip_sw_otp_ctrl_descrambling	15.771s		0	1	0.00
		chip_sw_pwrmgr_lowpower_cancel	14.227s		0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	14.160s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	14.011s		0	1	0.00
		TOTAL			25	326	7.67

Failure Buckets

• Job returned non-zero exit code has 298 failures:

  • Test chip_sw_example_flash has 1 failures.

    • 0.chip_sw_example_flash.82804386783141337226286400896943125478965793965604534698027689315508352198917
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log

                    done; \
                fi; \
            fi; \
        done;
        Building SW image "//sw/device/tests:example_test_from_flash_sim_dv".
        Building "//sw/device/tests:example_test_from_flash_sim_dv" on network connected machine.
        Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_test_from_flash_sim_dv
        Computing main repo mapping:
        ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32
      

  • Test chip_sw_example_rom has 1 failures.

    • 0.chip_sw_example_rom.20917810841866946220446289770728654713939346521931582777181476055426471087901
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'lowrisc_misc_linters+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp16207998266954051757/20250217_01.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp16207998266954051757/20250217_01.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • Test chip_sw_example_manufacturer has 1 failures.

    • 0.chip_sw_example_manufacturer.3402509243449795926834990125516055016489050010139515877543951189933682952490
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'lowrisc_misc_linters+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp9624122408730122645/20250217_01.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp9624122408730122645/20250217_01.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • Test chip_sw_example_concurrency has 1 failures.

    • 0.chip_sw_example_concurrency.35931602206052350014846333106371343003501582607697065084881718800204008960197
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'lowrisc_misc_linters+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp16805770746755231479/20250217_01.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp16805770746755231479/20250217_01.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • Test chip_sival_flash_info_access has 1 failures.

    • 0.chip_sival_flash_info_access.45908275681615745021548735690808950456466504343864488612886292427219280730499
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_multitool+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp17296885706800187167/temp-fork-0.4.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp17296885706800187167/temp-fork-0.4.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • ... and 293 more tests.

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38858) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.62461086842018094160573665165880198827211078913761289830429006260498134991937
      Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

        UVM_ERROR @ 2440.670450 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38858) { a_addr: 'h105e4  a_data: 'he4ad80dc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h19ee9  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2440.670450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:

  • Test chip_rv_dm_lc_disabled has 1 failures.

    • 0.chip_rv_dm_lc_disabled.88684818623567440132274769293098627276536811639461964158266444386569110179297
      Line 279, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

        UVM_ERROR @ 11907.239400 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10630 read out mismatch
        UVM_INFO @ 11907.239400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31790) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.chip_csr_mem_rw_with_rand_reset.80123753704120352842160746245101690469956794825962204854123996055714530054612
      Line 231, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2437.071977 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31790) { a_addr: 'h10340  a_data: 'h5710acd4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1a243  d_param: 'h0  d_source: 'ha  d_data: 'hc55513  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd33  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2437.071977 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---