ADC_CTRL Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	6.610s	5.901ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.630s	1.054ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.760s	559.646us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	13.950s	15.314ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.580s	1.101ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.360s	390.277us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.760s	559.646us	1	1	100.00
		adc_ctrl_csr_aliasing	2.580s	1.101ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	54.850s	327.400ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	8.342m	325.688ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	6.990m	488.542ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.642m	326.310ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	13.199m	435.258ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	3.805m	190.669ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.781m	165.932ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	4.518m	347.009ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.480s	2.917ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	53.810s	34.896ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.099m	79.859ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	9.972m	335.086ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	0.870s	385.664us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.180s	418.387us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.120s	408.443us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.120s	408.443us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.630s	1.054ms	1	1	100.00
		adc_ctrl_csr_rw	1.760s	559.646us	1	1	100.00
		adc_ctrl_csr_aliasing	2.580s	1.101ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.500s	2.159ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.630s	1.054ms	1	1	100.00
		adc_ctrl_csr_rw	1.760s	559.646us	1	1	100.00
		adc_ctrl_csr_aliasing	2.580s	1.101ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.500s	2.159ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	6.360s	4.103ms	1	1	100.00
		adc_ctrl_tl_intg_err	15.380s	7.624ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	15.380s	7.624ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.430s	5.752ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00