AES/MASKED Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	100.348us	1	1	100.00
V1	smoke	aes_smoke	3.000s	188.264us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.000s	69.131us	1	1	100.00
V1	csr_rw	aes_csr_rw	2.000s	90.545us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	13.230ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	141.383us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	85.540us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	90.545us	1	1	100.00
		aes_csr_aliasing	3.000s	141.383us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	3.000s	188.264us	1	1	100.00
		aes_config_error	2.000s	164.206us	1	1	100.00
		aes_stress	4.000s	337.002us	1	1	100.00
V2	key_length	aes_smoke	3.000s	188.264us	1	1	100.00
		aes_config_error	2.000s	164.206us	1	1	100.00
		aes_stress	4.000s	337.002us	1	1	100.00
V2	back2back	aes_stress	4.000s	337.002us	1	1	100.00
		aes_b2b	9.000s	533.514us	1	1	100.00
V2	backpressure	aes_stress	4.000s	337.002us	1	1	100.00
V2	multi_message	aes_smoke	3.000s	188.264us	1	1	100.00
		aes_config_error	2.000s	164.206us	1	1	100.00
		aes_stress	4.000s	337.002us	1	1	100.00
		aes_alert_reset	4.000s	226.510us	1	1	100.00
V2	failure_test	aes_man_cfg_err	2.000s	56.510us	1	1	100.00
		aes_config_error	2.000s	164.206us	1	1	100.00
		aes_alert_reset	4.000s	226.510us	1	1	100.00
V2	trigger_clear_test	aes_clear	4.000s	572.743us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	403.549us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	226.510us	1	1	100.00
V2	stress	aes_stress	4.000s	337.002us	1	1	100.00
V2	sideload	aes_stress	4.000s	337.002us	1	1	100.00
		aes_sideload	3.000s	158.748us	1	1	100.00
V2	deinitialization	aes_deinit	3.000s	282.529us	1	1	100.00
V2	stress_all	aes_stress_all	41.000s	3.510ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	67.768us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	68.512us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	68.512us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.000s	69.131us	1	1	100.00
		aes_csr_rw	2.000s	90.545us	1	1	100.00
		aes_csr_aliasing	3.000s	141.383us	1	1	100.00
		aes_same_csr_outstanding	2.000s	326.475us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.000s	69.131us	1	1	100.00
		aes_csr_rw	2.000s	90.545us	1	1	100.00
		aes_csr_aliasing	3.000s	141.383us	1	1	100.00
		aes_same_csr_outstanding	2.000s	326.475us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	2.000s	142.631us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	485.155us	1	1	100.00
		aes_control_fi	2.000s	341.784us	1	1	100.00
		aes_cipher_fi	17.000s	10.022ms	0	1	0.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	123.784us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	123.784us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	123.784us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	123.784us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	764.683us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	559.654us	1	1	100.00
		aes_tl_intg_err	3.000s	354.149us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	354.149us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	226.510us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	123.784us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	188.264us	1	1	100.00
		aes_stress	4.000s	337.002us	1	1	100.00
		aes_alert_reset	4.000s	226.510us	1	1	100.00
		aes_core_fi	4.000s	162.139us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	123.784us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	81.849us	1	1	100.00
		aes_stress	4.000s	337.002us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	337.002us	1	1	100.00
		aes_sideload	3.000s	158.748us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	81.849us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	81.849us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	81.849us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	81.849us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	81.849us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	337.002us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	337.002us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	485.155us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	485.155us	1	1	100.00
		aes_control_fi	2.000s	341.784us	1	1	100.00
		aes_cipher_fi	17.000s	10.022ms	0	1	0.00
		aes_ctr_fi	2.000s	49.345us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	485.155us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	485.155us	1	1	100.00
		aes_control_fi	2.000s	341.784us	1	1	100.00
		aes_cipher_fi	17.000s	10.022ms	0	1	0.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	17.000s	10.022ms	0	1	0.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	485.155us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	485.155us	1	1	100.00
		aes_control_fi	2.000s	341.784us	1	1	100.00
		aes_ctr_fi	2.000s	49.345us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	485.155us	1	1	100.00
		aes_control_fi	2.000s	341.784us	1	1	100.00
		aes_cipher_fi	17.000s	10.022ms	0	1	0.00
		aes_ctr_fi	2.000s	49.345us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	226.510us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	485.155us	1	1	100.00
		aes_control_fi	2.000s	341.784us	1	1	100.00
		aes_cipher_fi	17.000s	10.022ms	0	1	0.00
		aes_ctr_fi	2.000s	49.345us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	485.155us	1	1	100.00
		aes_control_fi	2.000s	341.784us	1	1	100.00
		aes_cipher_fi	17.000s	10.022ms	0	1	0.00
		aes_ctr_fi	2.000s	49.345us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	485.155us	1	1	100.00
		aes_control_fi	2.000s	341.784us	1	1	100.00
		aes_ctr_fi	2.000s	49.345us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	485.155us	1	1	100.00
		aes_control_fi	2.000s	341.784us	1	1	100.00
		aes_cipher_fi	17.000s	10.022ms	0	1	0.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.000s	2.942ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_cipher_fi has 1 failures.

    • 0.aes_cipher_fi.42854126924413048419224604034963199451275897804594619610397297369524915741179
      Line 141, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_cipher_fi/latest/run.log

        UVM_FATAL @ 10021562630 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10021562630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.96927869663553405082541196704803365535718699107601590742944507234604984693029
      Line 844, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 2941675221 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 2941675221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---