EDN Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.870s	53.985us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.880s	15.013us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.690s	46.686us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.670s	68.926us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.000s	27.701us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.080s	26.397us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.690s	46.686us	1	1	100.00
		edn_csr_aliasing	1.000s	27.701us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.190s	45.713us	1	1	100.00
V2	csrng_commands	edn_genbits	1.190s	45.713us	1	1	100.00
V2	genbits	edn_genbits	1.190s	45.713us	1	1	100.00
V2	interrupts	edn_intr	1.150s	23.322us	1	1	100.00
V2	alerts	edn_alert	1.020s	52.795us	1	1	100.00
V2	errs	edn_err	0.850s	31.837us	1	1	100.00
V2	disable	edn_disable	0.970s	14.297us	1	1	100.00
		edn_disable_auto_req_mode	1.060s	95.534us	1	1	100.00
V2	stress_all	edn_stress_all	4.150s	643.070us	1	1	100.00
V2	intr_test	edn_intr_test	0.800s	24.013us	1	1	100.00
V2	alert_test	edn_alert_test	0.860s	90.704us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.950s	138.450us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.950s	138.450us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.880s	15.013us	1	1	100.00
		edn_csr_rw	0.690s	46.686us	1	1	100.00
		edn_csr_aliasing	1.000s	27.701us	1	1	100.00
		edn_same_csr_outstanding	1.160s	33.805us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.880s	15.013us	1	1	100.00
		edn_csr_rw	0.690s	46.686us	1	1	100.00
		edn_csr_aliasing	1.000s	27.701us	1	1	100.00
		edn_same_csr_outstanding	1.160s	33.805us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	5.540s	892.841us	1	1	100.00
		edn_tl_intg_err	1.890s	127.386us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.820s	56.804us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.020s	52.795us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.540s	892.841us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.540s	892.841us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.540s	892.841us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.540s	892.841us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.020s	52.795us	1	1	100.00
		edn_sec_cm	5.540s	892.841us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.020s	52.795us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.890s	127.386us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	18.100s	1.111ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00