HMAC Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.340s 2.699ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.820s 28.747us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.750s 51.037us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.160s 735.634us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.180s 117.520us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 3.163m 77.070ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.750s 51.037us 1 1 100.00
hmac_csr_aliasing 2.180s 117.520us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 50.020s 17.102ms 1 1 100.00
V2 back_pressure hmac_back_pressure 53.670s 5.235ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.960s 358.622us 1 1 100.00
hmac_test_sha384_vectors 5.116m 17.839ms 1 1 100.00
hmac_test_sha512_vectors 6.561m 13.622ms 1 1 100.00
hmac_test_hmac256_vectors 6.380s 200.856us 1 1 100.00
hmac_test_hmac384_vectors 11.240s 1.300ms 1 1 100.00
hmac_test_hmac512_vectors 8.790s 955.620us 1 1 100.00
V2 burst_wr hmac_burst_wr 15.090s 1.608ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 17.940s 909.705us 1 1 100.00
V2 error hmac_error 1.682m 31.132ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 22.450s 2.349ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.340s 2.699ms 1 1 100.00
hmac_long_msg 50.020s 17.102ms 1 1 100.00
hmac_back_pressure 53.670s 5.235ms 1 1 100.00
hmac_datapath_stress 17.940s 909.705us 1 1 100.00
hmac_burst_wr 15.090s 1.608ms 1 1 100.00
hmac_stress_all 6.177m 39.318ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.340s 2.699ms 1 1 100.00
hmac_long_msg 50.020s 17.102ms 1 1 100.00
hmac_back_pressure 53.670s 5.235ms 1 1 100.00
hmac_datapath_stress 17.940s 909.705us 1 1 100.00
hmac_wipe_secret 22.450s 2.349ms 1 1 100.00
hmac_test_sha256_vectors 9.960s 358.622us 1 1 100.00
hmac_test_sha384_vectors 5.116m 17.839ms 1 1 100.00
hmac_test_sha512_vectors 6.561m 13.622ms 1 1 100.00
hmac_test_hmac256_vectors 6.380s 200.856us 1 1 100.00
hmac_test_hmac384_vectors 11.240s 1.300ms 1 1 100.00
hmac_test_hmac512_vectors 8.790s 955.620us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.340s 2.699ms 1 1 100.00
hmac_long_msg 50.020s 17.102ms 1 1 100.00
hmac_back_pressure 53.670s 5.235ms 1 1 100.00
hmac_datapath_stress 17.940s 909.705us 1 1 100.00
hmac_burst_wr 15.090s 1.608ms 1 1 100.00
hmac_error 1.682m 31.132ms 1 1 100.00
hmac_wipe_secret 22.450s 2.349ms 1 1 100.00
hmac_test_sha256_vectors 9.960s 358.622us 1 1 100.00
hmac_test_sha384_vectors 5.116m 17.839ms 1 1 100.00
hmac_test_sha512_vectors 6.561m 13.622ms 1 1 100.00
hmac_test_hmac256_vectors 6.380s 200.856us 1 1 100.00
hmac_test_hmac384_vectors 11.240s 1.300ms 1 1 100.00
hmac_test_hmac512_vectors 8.790s 955.620us 1 1 100.00
hmac_stress_all 6.177m 39.318ms 1 1 100.00
V2 stress_all hmac_stress_all 6.177m 39.318ms 1 1 100.00
V2 alert_test hmac_alert_test 0.870s 13.251us 1 1 100.00
V2 intr_test hmac_intr_test 0.630s 50.097us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.810s 90.955us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.810s 90.955us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.820s 28.747us 1 1 100.00
hmac_csr_rw 0.750s 51.037us 1 1 100.00
hmac_csr_aliasing 2.180s 117.520us 1 1 100.00
hmac_same_csr_outstanding 2.290s 484.133us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.820s 28.747us 1 1 100.00
hmac_csr_rw 0.750s 51.037us 1 1 100.00
hmac_csr_aliasing 2.180s 117.520us 1 1 100.00
hmac_same_csr_outstanding 2.290s 484.133us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.910s 141.441us 1 1 100.00
hmac_tl_intg_err 1.450s 363.885us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.450s 363.885us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.340s 2.699ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.880s 175.865us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.849m 40.081ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.000s 134.645us 1 1 100.00
TOTAL 28 28 100.00