I2C Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	49.540s	2.998ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	12.330s	4.546ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.790s	56.582us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.860s	215.597us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.150s	925.689us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.000s	418.470us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.770s	40.025us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.860s	215.597us	1	1	100.00
		i2c_csr_aliasing	1.000s	418.470us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.900s	15.886us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all			0	1	0.00
V2	host_maxperf	i2c_host_perf	1.805m	6.319ms	1	1	100.00
V2	host_override	i2c_host_override	0.710s	122.089us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.535m	18.992ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.481m	12.433ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.890s	153.987us	1	1	100.00
		i2c_host_fifo_fmt_empty	18.800s	2.031ms	1	1	100.00
		i2c_host_fifo_reset_rx	10.180s	277.226us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.030m	15.404ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	8.560s	1.617ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.950s	111.385us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.440s	1.254ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	35.970s	60.614ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.280s	638.821us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	36.790s	12.383ms	1	1	100.00
		i2c_target_intr_smoke	2.820s	2.420ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.950s	232.200us	1	1	100.00
		i2c_target_fifo_reset_tx	1.130s	505.391us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.681m	50.424ms	1	1	100.00
		i2c_target_stress_rd	36.790s	12.383ms	1	1	100.00
		i2c_target_intr_stress_wr	2.939m	25.199ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.860s	1.454ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	31.400s	4.348ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.980s	1.712ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	5.330s	10.141ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.590s	2.148ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.100s	197.506us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.805m	6.319ms	1	1	100.00
		i2c_host_perf_precise	6.570s	206.252us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	8.560s	1.617ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.010s	118.023us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.420s	2.247ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.830s	552.082us	1	1	100.00
		i2c_target_nack_txstretch	1.790s	729.792us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.830s	799.381us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.600s	459.603us	1	1	100.00
V2	alert_test	i2c_alert_test	0.610s	18.392us	1	1	100.00
V2	intr_test	i2c_intr_test	0.790s	66.826us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.040s	164.675us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.040s	164.675us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.790s	56.582us	1	1	100.00
		i2c_csr_rw	0.860s	215.597us	1	1	100.00
		i2c_csr_aliasing	1.000s	418.470us	1	1	100.00
		i2c_same_csr_outstanding	0.820s	106.002us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.790s	56.582us	1	1	100.00
		i2c_csr_rw	0.860s	215.597us	1	1	100.00
		i2c_csr_aliasing	1.000s	418.470us	1	1	100.00
		i2c_same_csr_outstanding	0.820s	106.002us	1	1	100.00
V2		TOTAL			32	38	84.21
V2S	tl_intg_err	i2c_tl_intg_err	1.410s	54.534us	1	1	100.00
		i2c_sec_cm	1.010s	239.973us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.410s	54.534us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	8.730s	841.222us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.220s	48.976us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.740s	2.638ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			41	50	82.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.19891260670403204036501903151228095061599575168942101504530637970515114024078
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  15886123 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  15886123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.24574069419073889951714573138393179730149613825211595438347463123672871712527
      Line 92, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2637592024 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 2637592024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.84757450167060355234203212758006998271710791371004902563551021218755147454827
      Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.76564393093250929275769817950911575753992670471932838622498037116455632122677
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1254294085 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1254294085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.115157638356807816975290118358306563679722962658253125242546108362506890443730
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  48975526 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 32 [0x20])
        UVM_INFO @  48975526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.67127495841610685497340035791807097628585520037235370997488369241884862874734
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10140548143 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10140548143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.111980264717930135404869556403173834317006245947856748866534209158493899380149
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 841222059 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 841222059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.50634022410931997436851348481199017520471538938980608965689143414847986211415
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @ 111384937 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x55497694, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 111384937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.92729407980528916079528275329239890610651146264858718724909051466915577090838
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 729791714 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 729791714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---