KMAC/UNMASKED Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	32.410s	956.864us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.010s	78.357us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.060s	32.005us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.190s	617.241us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.180s	755.786us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.250s	25.585us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.060s	32.005us	1	1	100.00
		kmac_csr_aliasing	6.180s	755.786us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.970s	38.686us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.400s	58.467us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	19.676m	378.364ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.463m	154.502ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	21.544m	75.107ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.260s	1.680ms	1	1	100.00
		kmac_test_vectors_sha3_384	15.990s	413.841us	1	1	100.00
		kmac_test_vectors_sha3_512	9.949m	9.426ms	1	1	100.00
		kmac_test_vectors_shake_128	23.450m	20.696ms	1	1	100.00
		kmac_test_vectors_shake_256	1.471m	4.767ms	1	1	100.00
		kmac_test_vectors_kmac	2.300s	230.887us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.200s	553.414us	1	1	100.00
V2	sideload	kmac_sideload	1.321m	13.966ms	1	1	100.00
V2	app	kmac_app	43.460s	8.633ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.610s	883.588us	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	47.700s	6.340ms	1	1	100.00
V2	error	kmac_error	1.075m	5.613ms	1	1	100.00
V2	key_error	kmac_key_error	7.780s	1.376ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.430s	2.124ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	15.920s	317.751us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	24.150s	461.745us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	8.300s	851.727us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.400s	142.899us	1	1	100.00
V2	stress_all	kmac_stress_all	1.637m	3.442ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.700s	26.225us	1	1	100.00
V2	alert_test	kmac_alert_test	0.900s	42.157us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.390s	411.781us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.390s	411.781us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.010s	78.357us	1	1	100.00
		kmac_csr_rw	1.060s	32.005us	1	1	100.00
		kmac_csr_aliasing	6.180s	755.786us	1	1	100.00
		kmac_same_csr_outstanding	1.480s	65.371us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.010s	78.357us	1	1	100.00
		kmac_csr_rw	1.060s	32.005us	1	1	100.00
		kmac_csr_aliasing	6.180s	755.786us	1	1	100.00
		kmac_same_csr_outstanding	1.480s	65.371us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	120.749us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	120.749us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	120.749us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	120.749us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.890s	180.175us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	24.300s	2.232ms	1	1	100.00
		kmac_tl_intg_err	3.090s	1.743ms	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.090s	1.743ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.400s	142.899us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	32.410s	956.864us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.321m	13.966ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	120.749us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	24.300s	2.232ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	24.300s	2.232ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	24.300s	2.232ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	32.410s	956.864us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.400s	142.899us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	24.300s	2.232ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.409m	2.328ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	32.410s	956.864us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.559m	70.519ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.101145934958127823557040425148467922241019112197096861069739237247342180028956
      Line 220, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 70518642332 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 70518642332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---