PATTGEN Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	3.000s	22.329us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	13.145us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	50.751us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	224.147us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	48.537us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.000s	27.816us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	50.751us	1	1	100.00
		pattgen_csr_aliasing	1.000s	48.537us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	3.283m	98.441ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	10.000s	3.588ms	1	1	100.00
V2	error	pattgen_error	2.000s	279.608us	1	1	100.00
V2	stress_all	pattgen_stress_all	3.000s	532.021us	1	1	100.00
V2	alert_test	pattgen_alert_test	1.000s	57.867us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	48.292us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	162.152us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	162.152us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	13.145us	1	1	100.00
		pattgen_csr_rw	2.000s	50.751us	1	1	100.00
		pattgen_csr_aliasing	1.000s	48.537us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	36.602us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	13.145us	1	1	100.00
		pattgen_csr_rw	2.000s	50.751us	1	1	100.00
		pattgen_csr_aliasing	1.000s	48.537us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	36.602us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.000s	171.244us	1	1	100.00
		pattgen_sec_cm	1.000s	120.168us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.000s	171.244us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	25.000s	13.110ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	1.000s	157.393us	1	1	100.00
		TOTAL			17	18	94.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.77447503809927286184943279964118518892464274718643445522543206393812995708654
      Line 136, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1388305038 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1388327231 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1388327231 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 1388410565 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]