ROM_CTRL/32KB Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.510s	184.481us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.380s	347.114us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.210s	179.560us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.640s	384.787us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.570s	610.304us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.070s	136.352us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.210s	179.560us	1	1	100.00
		rom_ctrl_csr_aliasing	4.570s	610.304us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.610s	534.575us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.980s	2.005ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	4.150s	232.693us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	12.370s	2.880ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.800s	1.513ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.610s	298.275us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.850s	310.426us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.850s	310.426us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.380s	347.114us	1	1	100.00
		rom_ctrl_csr_rw	5.210s	179.560us	1	1	100.00
		rom_ctrl_csr_aliasing	4.570s	610.304us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.200s	535.621us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.380s	347.114us	1	1	100.00
		rom_ctrl_csr_rw	5.210s	179.560us	1	1	100.00
		rom_ctrl_csr_aliasing	4.570s	610.304us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.200s	535.621us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.054m	28.774ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	14.710s	588.699us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.675m	1.438ms	0	1	0.00
		rom_ctrl_tl_intg_err	24.690s	458.305us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.675m	1.438ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.675m	1.438ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.054m	28.774ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.054m	28.774ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.054m	28.774ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.054m	28.774ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.054m	28.774ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.675m	1.438ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.675m	1.438ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.510s	184.481us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.510s	184.481us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.510s	184.481us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	24.690s	458.305us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.054m	28.774ms	1	1	100.00
		rom_ctrl_kmac_err_chk	8.800s	1.513ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.054m	28.774ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.054m	28.774ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.054m	28.774ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	14.710s	588.699us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.675m	1.438ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	7.479m	6.170ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.54080011344153314328718270283922513740035782810396778619000734136321649073756
      Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 3609081ps failed at 3609081ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 3654536ps failed at 3654536ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'