ce6e476| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 1.040s | 26.358us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.810s | 54.955us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.840s | 15.517us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.540s | 219.716us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 1.000s | 18.721us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.990s | 62.673us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.840s | 15.517us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 1.000s | 18.721us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 3.770s | 7.165ms | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 1.330s | 3.192ms | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 6.190s | 8.298ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 6.190s | 8.298ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 3.960s | 1.047ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.750s | 10.812us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.630s | 35.308us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.070s | 205.734us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.070s | 205.734us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.810s | 54.955us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.840s | 15.517us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 1.000s | 18.721us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.000s | 32.145us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.810s | 54.955us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.840s | 15.517us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 1.000s | 18.721us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.000s | 32.145us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.530s | 428.743us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 0.850s | 48.564us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.850s | 48.564us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 0.630s | 72.898us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.750s | 84.491us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 39.140s | 9.007ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 3 | 33.33 | |||
| TOTAL | 16 | 19 | 84.21 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.29597451626637394573432779707636151565697560193315939653802139208947568086224
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 72898208 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x27de9304) == 0x1
UVM_INFO @ 72898208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.7986702776738631913493957255588580876060623688166389540004974861266494651217
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 7164538409 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xdc72d04) == 0x1
UVM_INFO @ 7164538409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.1923588004660746062146103727616289839263168342447970832897738048176342689274
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 84490989 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 84490989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---