SPI_DEVICE/1R1W Simulation Results

Wednesday September 24 2025 17:31:32 UTC

GitHub Revision: ce6e476

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.234m	5.385ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.240s	25.095us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.790s	101.044us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.020s	2.176ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.310s	625.567us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.620s	123.230us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.790s	101.044us	1	1	100.00
		spi_device_csr_aliasing	14.310s	625.567us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.830s	37.185us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.880s	216.403us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.820s	62.459us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.070s	1.699us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.020s	4.382us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.250s	79.667us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.250s	79.667us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.790s	2.002ms	1	1	100.00
		spi_device_tpm_sts_read	1.080s	38.335us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.620s	1.960ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.340s	3.631ms	1	1	100.00
		spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.010s	355.683us	1	1	100.00
		spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.010s	355.683us	1	1	100.00
		spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.770s	2.054ms	1	1	100.00
		spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.770s	2.054ms	1	1	100.00
		spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.770s	2.054ms	1	1	100.00
		spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.770s	2.054ms	1	1	100.00
		spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.770s	2.054ms	1	1	100.00
		spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.210s	729.482us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	20.690s	3.948ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	20.690s	3.948ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	20.690s	3.948ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.930s	600.992us	1	1	100.00
		spi_device_read_buffer_direct	3.540s	305.896us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	20.690s	3.948ms	1	1	100.00
		spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.613m	22.909ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.410s	156.391us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.410s	156.391us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.234m	5.385ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.079m	8.362ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.946m	38.109ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.810s	41.638us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.760s	53.925us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.510s	483.321us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.510s	483.321us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.240s	25.095us	1	1	100.00
		spi_device_csr_rw	1.790s	101.044us	1	1	100.00
		spi_device_csr_aliasing	14.310s	625.567us	1	1	100.00
		spi_device_same_csr_outstanding	3.410s	830.379us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.240s	25.095us	1	1	100.00
		spi_device_csr_rw	1.790s	101.044us	1	1	100.00
		spi_device_csr_aliasing	14.310s	625.567us	1	1	100.00
		spi_device_same_csr_outstanding	3.410s	830.379us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	0.860s	38.887us	1	1	100.00
		spi_device_tl_intg_err	12.720s	292.670us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.720s	292.670us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.170s	56.302us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.19385399352960912994551122537052026653515786242713419450600302266081521183981
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    991924 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[43])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    991924 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    991924 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[939])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.87104000520803428410217562239229351154251327790834481698804430894719671586056
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1750817 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x25892f [1001011000100100101111] vs 0x0 [0])
        UVM_ERROR @   1803817 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdb2556 [110110110010010101010110] vs 0x0 [0])
        UVM_ERROR @   1833817 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb06416 [101100000110010000010110] vs 0x0 [0])
        UVM_ERROR @   1921817 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc59ec0 [110001011001111011000000] vs 0x0 [0])
        UVM_ERROR @   1944817 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8ccb74 [100011001100101101110100] vs 0x0 [0])